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The study proposes a new decision heuristic for Davis Putnam, Loveland and Logemann algorithm (DPLL)-based satisfiability (SAT) solvers based on cube subtraction. Each negated clause is viewed as a cube in the n-dimensional Boolean search space denoting a subspace where no satisfying assignments can be found. Cube subtraction systematically subtrac...
We propose a new algorithm for organizing the search in DPLL-based SAT solvers. Each negated clause is viewed as a cube in the n-dimensional Boolean search space denoting a sub-space where no satisfying assignments can be found. The algorithm systematically subtracts all clause-cubes from the universal cube that represents the entire n-dimensional...
The majority of the existing reconfigurable hardware SAT solvers employ some variation of the Davis-Putnam algorithm; we propose a new algorithm for organizing the search in SAT Solvers best suited to reconfigurable architectures due to its vector-like operations. Its essence is to view each negated clause as a cube in the n-dimensional Boolean sea...
Reconfigurable computers have demonstrated performance advantages over general-purpose processors for some classes of problems. However, some problems need hardware changes while in operation. A technique where a dynamic reconfiguration behavior was achieved using generic FPGA devices is shown in this work. A prototype of a reconfigurable tool for...