Rolf Kraemer

Rolf Kraemer
Institute for High Perfomance microelectronics and TU-Cottbus · Wireless Systems

PhD

About

250
Publications
22,397
Reads
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1,547
Citations
Additional affiliations
November 1998 - July 2014
Brandenburg University of Technology Cottbus - Senftenberg
Position
  • Professor (Full)

Publications

Publications (250)
Article
Full-text available
The key computation in the min-sum decoding algorithm of a Low-Density Parity-Check (LDPC) code is finding the first two minima and also the location of the first minimum among a set of messages passed from Variable Nodes (VNs) to Check Nodes (CNs) in a Tanner graph. In this paper, we propose a modified rejection-based scheme for this task which is...
Article
Full-text available
Layered decoding (LD) facilitates a partially parallel architecture for performing belief propagation (BP) algorithm for decoding low-density parity-check (LDPC) codes. Such a schedule for LDPC codes has, in general, reduced implementation complexity compared to a fully parallel architecture and higher convergence rate compared to both serial and p...
Conference Paper
This paper investigates coding and modulation schemes for wireless communication based on variable-rate parallel sequence spread spectrum (PSSS). PSSS can adapt the spreading gain according to channel conditions. When this modulation technique is combined with external forward error correction (FEC), a challenge arises in adjusting the gains from F...
Conference Paper
In this paper, we investigate the use of bipolar Barker sequences for high-speed wireless communication based on Parallel Sequence Spread Spectrum (PSSS) modulation. To improve bit error rate (BER) performance for PSSS, we propose median detection at the receiver or DC-offset correction at the transmitter. Both techniques cancel the influence of cy...
Article
This work investigates the use of pulse stretching (skew-sized) inverters for monitoring the variation of count rate and Linear Energy Transfer (LET) of energetic particles. The basic particle detector is a cascade of two pulse stretching inver-ters, and the required sensing area is obtained by connecting up to twelve two-inverter cells in parallel...
Preprint
Full-text available
The soft error rate (SER) of integrated circuits (ICs) operating in space environment may vary by several orders of magnitude due to the variable intensity of radiation exposure. To ensure the radiation hardness without compromising the system performance, it is necessary to implement the dynamic hardening mechanisms which can be activated under th...
Preprint
Full-text available
This work investigates the use of pulse stretching inverters for monitoring the variation of flux and Linear Energy Transfer (LET) of energetic particles. The basic particle detector consists of two cascaded pulse stretching (skew-sized) inverters designed in CMOS technology, and the required sensing area is obtained by connecting multiple two-inve...
Preprint
p>The key computation in the min-sum decoding algorithm of a Low-Density Parity-Check (LDPC) code is finding the first two minima and also the location of the first minimum among a set of messages passed from Variable Nodes (VNs) to Check Nodes (CNs) in a Tanner graph. In this paper, we propose a modified rejection-based scheme for this task which...
Preprint
p>The key computation in the min-sum decoding algorithm of a Low-Density Parity-Check (LDPC) code is finding the first two minima and also the location of the first minimum among a set of messages passed from Variable Nodes (VNs) to Check Nodes (CNs) in a Tanner graph. In this paper, we propose a modified rejection-based scheme for this task which...
Conference Paper
Standard delay cells (SDCs) are commonly used for timing synchronization in digital designs. Due to skewed transistor sizing, the SETs induced in SDCs may be stretched during propagation through the cell, thus increasing the soft error rate. In this work, the simulation analysis of Single Event Transient (SET) effects in 130 nm SDCs is presented. T...
Conference Paper
The soft error rate (SER) of integrated circuits (ICs) operating in space environment may vary by several orders of magnitude due to the variable intensity of radiation exposure. To ensure the radiation hardness without compromising the system performance, it is necessary to implement the dynamic hardening mechanisms, which can be activated under t...
Preprint
Full-text available
Layered decoding (LD) of Low-Density Parity-Check (LDPC) codes is a decoding schedule that facilitates partially parallel architectures for performing Belief Propagation (BP)-based iterative algorithms. It has reduced implementation complexity and memory overhead compared to fully parallel architectures and higher convergence speed compared to both...
Conference Paper
In this paper, a novel, highly configurable framework for low power and error-resilient System-On-Chip is presented. The framework is composed, on the one hand, of the SWIELD configurable flip-flop and on the other hand, of the Chameleon controller. The SWIELD flip-flop is able to operate in three modes. It is driven/configured during runtime via t...
Article
The implementation of Wireless Sensor Networks (WSNs) is a challenging task due to their intrinsic characteristics, e.g., energy limitations and unreliable wireless links. Considering this, we have developed the Disjoint path And Clustering Algorithm (DACA) that combines topology control and self-healing mechanisms to increase the network lifetime...
Conference Paper
Monitoring of energetic particles responsible for the soft errors is an important requirement in the design of fault-tolerant systems for space missions. In this paper, the use of a custom-sized CMOS pulse stretching inverter chain as a particle detector is studied. The proposed detector allows for measuring the particle flux in terms of the count...
Article
This article presents a fully integrated modular wideband frequency interleaving (FI) transmitter and receiver for high data rate communication applications. At the transmitter side, three independent in-phase and quadrature-phase (IQ) baseband channels are upconverted to different intermediate frequencies (IFs) and then interleaved. At the receive...
Conference Paper
With the rapid CMOS technology downscaling, two requirements for digital integrated circuits (ICs) design are becoming fundamental: low power consumption and error resilience. Many proposed solutions are effective either in reducing the power consumption or improving the error resilience, but a single approach that addresses both aspects seems to b...
Conference Paper
Single event transients (SETs) stand out as one of the major causes of soft errors in nanoscale CMOS integrated circuits. To reduce the need for exhaustive circuit simulations in the design of radiation-hard integrated circuits, the cost-effective approaches for characterization and modeling of SET generation effects in standard logic cells are req...
Article
Full-text available
Bluetooth was firstly announced in 1998. Originally designed as cable replacement connecting devices in a point-to-point fashion its high penetration arouses interest in its ad-hoc networking potential. This ad-hoc networking potential of Bluetooth is advertised for years - but until recently no actual products were available and less than a handfu...
Preprint
Full-text available
In this paper, we obtain and study typical beam entropy values for millimetre wave (mm-wave) channel models using the NYUSIM simulator for frequencies up to 100 GHz for fifth generation (5G) and beyond 5G cellular communication systems. The beam entropy is used to quantify sparse MIMO channel randomness in beamspace. Lower relative beam entropy cha...
Preprint
Full-text available
Terahertz spectrum is being researched upon to provide ultra-high throughput radio links for indoor applications, e.g., virtual reality (VR), etc. as well as outdoor applications, e.g., backhaul links, etc. This paper investigates a monopulse-based beam tracking approach for limited mobility users relying on sparse massive multiple input multiple o...
Preprint
Full-text available
This paper presents a novel radio frequency (RF) beam training algorithm for sparse multiple input multiple output (MIMO) channels using unitary RF beamforming codebooks at transmitter (Tx) and receiver (Rx). The algorithm leverages statistical knowledge from past beam data for expedited beam search with statistically-minimal training overheads. Be...
Article
We present the state-of-the-art related to self-organizing and self-healing techniques. On the one hand, self-organization is the nodes' ability to construct a network topology without any human intervention and any previous topology knowledge. On the other hand, self-healing is the network's ability to recover from failures by using hardware and s...
Article
Zusammenfassung Im Kontext von Industrie 4.0 werden verstärkt drahtlose Kommunikationssysteme in industrielle Anwendungen integriert. Die Anforderungen der Fertigungsautomation, welche besonders streng hinsichtlich Zuverlässigkeit und Latenz sind, werden bisher nur teilweise durch spezifische kabellose Systeme wie WirelessHART oder WSAN erfüllt. Da...
Article
In this paper, we show our 165 Gbps data link layer processor for wireless communication in the terahertz band. The design utilizes interleaved Reed-Solomon codes with dedicated link adaptation, fragmentation, aggregation, and hybrid-automatic-repeat-request. The main advantage is the low-chip area required to fabricate the processor, which is at l...
Conference Paper
This paper investigates the applicability of CMOS decoupling cells for mitigating the Single Event Transient (SET) effects in standard combinational gates. The concept is based on the insertion of two decoupling cells between the gate's output and the power/ground terminals. To verify the proposed hardening approach, extensive SPICE simulations hav...
Conference Paper
Full-text available
This paper addresses an uplink system configuration for an Industrial Environment, in addition, a novel robust and low-complexity space time code is proposed. Based on channel modelling of Quadriga which follows a geometry-based stochastic channel modeling approach, the proposed space time code is applied in the uplink of an industrial communicatio...
Conference Paper
The robustness of standard CMOS combinational logic gates to Single Event Transients (SETs), in the presence of resistive open and resistive bridge defects, was investigated. Analysis was performed with SPICE simulations, using the resistors for modeling the open and bridge defects, and a standard double-exponential current source for modeling the...
Conference Paper
Full-text available
High reliability and low power consumption are two fundamental requirements for design and implementation of many dependable systems. Improving reliability by employing redundancy increases the power consumption. On the other hand, reducing the power consumption through voltage scaling worsens the reliability. Multiprocessor systems provide good ba...
Article
This paper analyzes the normal response and the sensitivity to Single Event Transients (SETs) of a CMOS pulse stretching circuit used for the SET pulse width measurement. The pulse stretcher based on two cascaded asymmetrically sized inverters, designed in IHP's 130 and 250 nm bulk CMOS technologies, has been studied. Results from SPICE simulations...
Conference Paper
This paper presents a critical charge model for estimating the SET and SEU robustness. The proposed model has been derived by analytic fitting of SPICE results, using a Muller C-element designed in 65 and 130 nm bulk CMOS technologies as the target device. The critical charge is expressed in terms of the size of C-element, size of load inverter, su...
Conference Paper
Full-text available
In this paper, the single event transient (SET) effects in an inverter designed in 250 nm bulk CMOS technology have been investigated with the 2D TCAD simulations using Synopsys Sentaurus tool. The dependence of the SET voltage pulse at the output of inverter on the particle's LET, strike location, angle of incidence, supply voltage and temperature...
Article
Wireless communications is one of the fastest growing technology fields, driving numerous other innovations in electronics. One challenging research area within the wireless field is to achieve much higher transmission rates. First products with up to 3 Gb/s are in the market. In the coming years we predict this speed growing quickly up to and beyo...
Presentation
Full-text available
This presentation addresses the Radio and Network Resource Management (RNRM) for the emerging Heterogeneous Vehicular Networks (HetVNets). It surveys the current research literature in this field and propose some suggestion for future ones.
Article
This paper presents a link adaptation algorithm dedicated for 100 Gbps wireless transmission. Interleaved Reed-Solomon codes are selected as forward error correction (FEC) algorithms. The redundancy of the codes is selected according to the channel bit error rate (BER). The uncomplicated FEC scheme allows implementing a complete data link layer pro...
Conference Paper
Full-text available
The increasing disturbances affecting the electronic systems as a result of the aggressive technology downscaling forced the designers to search for cost-effective approaches that will enable handling various reliability threats at minimum costs. It is believed that cross-layer resilience techniques, i.e., resilience techniques implemented across m...
Article
Full-text available
Die Digitalisierung der Gesellschaft und Industrie schreitet unaufhörlich voran, und die Bedeutung des Zugangs zu uneingeschränkter mobiler Vernetzung für unser gesellschaftliches und berufliches Leben nimmt somit ebenfalls stetig zu. Mit der Entwicklung der 5G Mobilfunkgeneration, aber auch echtzeitfähiger lokaler Funknetze werden in Zukunft digit...
Article
In this article mixed analog/digital signal processing techniques based on parallel spread-spectrum sequencing (PSSS) and radio frequency (RF) carrier synchronization for ultra-broadband wireless communication are investigated on system and circuit level.
Article
100 Gbit/s wireless communication protocol processing stresses all parts of a communication system until the outermost. The efficient use of upcoming 100 Gbit/s and beyond transmission technology requires the rethinking of the way protocols are processed by the communication endpoints. This paper summarizes the achievements of the project End2End10...
Article
Full-text available
This paper presents a hardware processor for 100 Gbps wireless data link layer. A serial Reed-Solomon decoder requires a clock of 12.5 GHz to fulfill timings constraints of the transmission. Receiving a single Ethernet frame on a 100 Gbps physical layer may be faster than accessing DDR3 memory. Processing so fast streams on a state-of-the-art FPGA...
Conference Paper
In this paper we give an overview of the German project cluster FAST which targets a technical breakthrough by real-time with latencies below 1 ms to enable advanced applications in the area of connectivity, traffic, manufacturing and health. FAST is based on 25 technical projects conducted by over 80 partners in industry and research. The innovati...