Robert Brodersen

• University of California, Berkeley

mmWave (millimeter-Wave) is a very promising technology for the future wireless communication. To mitigate its high attenuation characteristics, mmWave communication frequently employs directional beamforming for both transmission and reception. Localization commonly takes advantage of directionality in RF frequencies in urban and indoor environmen...

In 1965, Gordon Moore observed that ?single-chip integrated circuits were doubling in complexity approximately every two years, mostly by reducing all dimensions of devices. He correctly foresaw the continuation of that trend for many years ahead. Following announcements of the first 1,024 bit memory chip (Intel 1103, in 1970) and the first micropr...

This chapter introduces the fundamentals of digital filter design, with emphasis on their usage in radio applications. Radios by definition are expected to transmit and receive signals at certain frequencies, while also ensuring that the transmission does not exceed a specified bandwidth. We will, therefore, discuss the usage of digital filters in...

This chapter discusses DSP techniques used to design digitally intensive front ends for radio systems. Conventional radio architectures use analog components and RF filters that do not scale well with technology, and have poor tunability required for supporting multiple modes of operation. Digital CMOS scales well in power, area, and speed with eac...

This chapter presents a design example of a kHz-rate neural processor. A brief introduction to kHz design will be provided, followed by an introduction to neural spike sorting. Several spike-sorting algorithms will be reviewed. Lastly, the design of a 130-μW, 64- channel spike-sorting DSP chip will be presented.

Automation of the architectural transformations introduced in Chap. 3 is discussed here. The reader will gain insight into how data-flow graphs are mathematically modeled as matrices and how transformations such as retiming, pipelining, parallelism and time-multiplexing are implemented at this level of abstraction. Reasonable understanding of algor...

This chapter studies architecture flexibility and its implication on energy and area efficiency. Having a flexible architecture would be nice. It would be convenient if we could design a chip and program it to do whatever it needs to do. There would be no need for optimizations prior to any design decisions. What is the cost of flexibility? What ar...

This chapter reviews number representation and DSP arithmetic. It starts with floating-point number representation. Fixed-point representations are then introduced, as well as related topics such as overflow and quantization modes. Basic implementations of add and multiply operations are shown as a baseline for studying the impact of micro-architec...

This chapter introduces energy and delay metrics of digital circuits used to implement DSP algorithms. The discussion begins with energy and delay definitions for logic gates, including the analysis of various factors that contribute to energy consumption and propagation delay. Design tradeoffs with respect to tuning gate size, supply and threshold...

This chapter studies iterative algorithms for division, square rooting, trigonometric and hyperbolic functions and their baseline architecture. Iterative approaches are suitable for implementing adaptive signal processing algorithms such as those found in wireless communications.

Having looked at algorithms for scheduling and retiming, we will now discuss an integrated design flow, which leverages these automation algorithms to create a user-friendly optimization framework. The flow is intended to address key challenges of ASIC design in scaled technologies: design complexity and design flexibility. Additionally, the design...

This chapter discusses various representations of DSP algorithms. We study how mathematical equations describing the algorithm functionality are translated into compact graphical models. These models enable efficient implementation of the algorithm in hardware while also enabling architectural transformations through matrix manipulations. Common ex...

This chapter discusses design techniques for dealing with design flexibility, in addition to complexity that was discussed in the previous chapter. Design techniques for managing adjustable number or antennas, modulations, number of sub-carriers and search algorithms will be presented. Multi-core architecture, based on scalable processing element w...

In this chapter we will discuss the methods for time frequency analysis and the DSP architectures for implementing these methods. In particular, we will use the FFT and the wavelet transform as our examples for this chapter. The well-known Fast Fourier Transform (FFT) is applicable to the frequency analysis of stationary signals. Wavelets provide a...

This chapter discusses methods for circuit-level optimization. We discuss a methodology for generating the optimal energy-delay tradeoff by tuning gate size and supply and threshold voltages. The methodology is based on the sensitivity approach to measure and balance the benefits of all the tuning variables. The analysis will be illustrated on data...

This chapter discusses wordlength optimization. Emphasis is placed on automated floating-to-fixed point conversion. Reduction in the number of bits without significant degradation in algorithm performance is an important step in hardware implementation of DSP algorithms. Manual tuning of bits is often performed by designers. Such approach is time-c...

This chapter will demonstrate hardware realization of multidimensional signal processing. The emphasis is on managing design complexity and minimizing power and area for complex signal processing algorithms. As an example, adaptive algorithm for singular value decomposition will be used. Power and area efficiency derived from this example will also...

This chapter discusses architectural techniques for area and energy reduction in chips for digital signal processing. Parallelism, time-multiplexing, pipelining, interleaving and folding are compared in the energy-delay space of pipeline logic as a systematic way to evaluate different architectural options. The energy-delay analysis is extended to...

Recently, the concept of “personal communications” has come to the forefront of communications research, in which individual users will have portable, private access to fixed computing facilities. The ultimate goal is to provide a personal communications system (PCS), which will move information of all kinds to and from people in all locations, thr...

This paper presents an automated tool for floating-point to fixed-point conversion. The tool is based on previous work that was built in MATLAB/Simulink environment and Xilinx System Generator support. The tool is now extended to include Synplify DSP blocksets in a seamless way from the users' view point. In addition to FPGA area estimation, the to...

An asynchronous 6 bit 1 GS/s ADC is achieved by time interleaving two ADCs based on the binary successive approximation (SA) algorithm using a series capacitive ladder. The semi-closed loop asynchronous technique eliminates the high internal clocks and significantly speeds up the SA algorithm. A key feature to reduce the power in this design involv...

A low-power mixed-signal baseband analog front-end for 60 GHz, 1 Gb/s wireless communications has been implemented in a standard 90 nm CMOS process. The receiver is capable of operating under indoor multipath scenarios, resolving channels with up to 32 ns multipath delay spread. It uses mixed-signal equalization and carrier recovery in order to min...

low-power UWB hardware;analog to digital (A/D) and digital to analog (D/A) converters;CMOS implementations;UWB radios and new circuit blocks and combinations of blocks;low-rate radios capable of communication and ranging;OFDM and pulse-based architectures

This chapter describes a high-performance image-processing system by using Simulink and mapping to a field programmable gate array (FPGA)-based platform using a design flow built around the Xilinx system generator tools. The system implements edge detection in real time on a digitized video stream and produces a corresponding video stream labeling...

A 100 MS/s pipelined ADC is digitally calibrated by a slow SigmaDelta ADC using a least-mean-square (LMS) algorithm. Both linear and nonlinear memoryless residue gain errors of the pipeline stages are adaptively corrected. With a 411 kHz sinusoidal input, the peak SNDR improves from 28 dB to 59 dB and the SFDR improves from 29 dB to 68 dB. The comp...

Large-scale, direct-mapped FPGA computing systems are traditionally very difficult to debug due to the high level of parallelism and limited access to internal signal values. In our approach to mitigate this problem, the concepts of variables and process control are brought into the FPGA hardware domain. Declarations made in the design environment...

This paper presents the design and implementation of BORPHpsilas kernel file system layer that provides FPGA processes direct access to the general file system. Using a semantics resembling that of conventional UNIX file I/Os, an FPGA accesses the file system through a special hardware system call interface. By extending the semantics of a UNIX pip...

A low-power, mixed-signal, baseband analog front end for 60 GHz 1 Gb/s wireless communications has been implemented in a standard 90 nm CMOS process. The receiver is capable of operating under indoor multipath scenarios, resolving channels with up to 32 ns multipath delay spread. It uses mixed-signal equalization and carrier recovery in order to mi...

This paper presents the design of BORPH's file system layer for FPGA-based reconfigurable computers. BORPH provides user FPGA designs that execute as hardware processes access to the general file system using familiar UNIX file I/O semantics. Such capability provides FPGA designers an intuitive interface not only for regular file I/O, but also for...

This paper explores the design and implementation of BORPH, an operating system designed for FPGA-based reconfigurable computers. Hardware designs execute as normal UNIX processes under BORPH, having access to standard OS services, such as file system support. Hardware and software components of user designs may, therefore, run as communicating pro...

Flexible radio testbeds are being designed using the Berkeley Emulation Engine (BEE2) platform. Narrow-band and wide-band platforms are discussed which can accommodate a full spectrum of wireless multiple radios for wide and narrowband applications. The BEE2 programming and debugging capabilities, using Simulink and Linux augmented with the BORPH o...

An impulse radio architecture utilizing a simple analog front end along with digital complex signal processing is proposed to allow a low complexity implementation of a 3.1-10.6 GHz ultrawideband (UWB) radio. The proposed system transmits passband pulses using a pulser and antenna, and the receiver front-end downconverts the signal frequency via su...

Cognitive radio technology enables the opportunistic operation of secondary devices in frequency bands allocated to primary users. In this paper we explore how this technology can enable ultra-wideband (UWB) systems to coexist with primary users. The distinguishing aspect of cognitive radio technology is the ability to detect and avoid primary user...

A unified algorithm-architecture-circuit co-design environment for dedicated signal processing hardware is presented. The approach is based on a single design description in the graphical Matlab/Simulink environment that is used for FPGA emulation, ASIC design, verification and chip testing. This unified description enables system designer with a v...

The discrepancy between perceived spectrum shortage from the FCC allocation map and the actual abundance of available spectrum is a motivation for Cognitive Radios, which locate and transmit in the unused or lightly used bands. If a digital approach is taken to provide the necessary radio flexibility to exploit this sparsity, there is a challenging...

Ultra-wideband (UWB) impulse radio is a promising technique for low-power bio-medical communication systems. While a range of analog and digital UWB architectures exist, the mostly-digital approach without analog down-conversion enables better technology scaling and signal processing flexibility. Furthermore, recently proposed sub-sampling schemes...

Cognitive radios have been advanced as a technology for the opportunistic use of underutilized spectrum wherein secondary devices sense the presence of the primary user and use the spectrum only if it is deemed empty. Spectral cognition of this form can also be used by regulators to facilitate the dynamic coexistence of different service types. An...

This paper presents a comprehensive characterization of cyclostationary feature detectors through theoretical analysis, hardware implementation, and real-time performance measurements. Results of our study show that feature detectors are highly susceptible to sampling clock offsets. We propose a new detector that overcomes this limitation, and char...

Cognitive radios have been advanced as a technology for the opportunistic use of under-utilized spectrum wherein secondary devices sense the presence of the primary user and use the spectrum only if it is deemed empty. The distinguishing aspect of cognitive radios is the ability to sense the primary user and modify their transmission parameters to...

Sensitivity-based methodology is applied to optimization of performance, power and area across several levels of design abstraction for a complex wireless baseband signal processing algorithm. The design framework is based on a unified, block-based graphical description of the algorithm to avoid design re-entry in various phases of chip development...

Antenna arrays are becoming increasingly important as wireless systems are moving to higher frequencies and implementation in CMOS. Advanced CMOS wireless systems leverage the vast computation resources available in the technology, and so simple digital phase shifters are preferred. This introduces significant quantization errors in the antenna pat...

A 60GHz CMOS front-end receiver is described. The receiver comprises an LNA, a quadrature-balanced downconversion mixer, a VCO, and a frequency doubler. The integrated front-end has a conversion gain of 11.8dB, an NF of 10.4dB, and an input P_1dB of -15.8dBm. The receiver is implemented in a digital 0.13mum CMOS process and draws 64mA fro...

Recently, cognitive radios have been proposed as a possible solution to improve spectrum utilization via opportunistic spectrum sharing. Cognitive radios are considered lower priority or secondary users of spectrum allocated to a primary user. Their fundamental requirement is to avoid interference to potential primary users in their vicinity. Spect...

An asynchronous analog-to-digital converter (ADC) based on successive approximation is used to provide a high-speed (600-MS/s) and medium-resolution (6-bit) conversion. A high input bandwidth (>4 GHz) was achieved which allows its use in RF subsampling applications. By using asynchronous processing techniques, it avoids clocks at higher than the sa...

In the process of designing adaptive wireless communication systems, the design cycle traditionally requires re-entering a design at various abstraction levels, constraining the implementation choices and increasing time-to-market. An approach to use a unified design description for algorithm verification and architecture exploration is presented....

The idea of cognitive radios has created a great interest in academic and industrial research. As a result, there are a large number of proposals for their physical and network layer functionalities. However, most of these research results rely on a theoretical analysis or computer simulations. In order to enable this technology and fully understan...

There are several new radio systems which exploit novel strategies being made possible by the regulatory agencies to increase the availability of spectrum for wireless applications. Three of these that will be discussed are ultra-wideband (UWB), 60 GHz, and cognitive radios. The UWB approach attempts to share the spectrum with higher-priority users...

This paper presents a sub-mW ultra-wideband (UWB) fully differential CMOS low-noise amplifier (LNA) operating below 960 MHz for sensor network applications. By utilizing both nMOS and pMOS transistors to boost the transconductance, coupling the input signals to the back-gates of the transistors, and combining the common-gate and shunt-feedback topo...

This paper presents a hw/sw codesign methodology based on BORPH, an operating system designed for FPGA-based reconfigurable computers (RC's). By providing native kernel support for FPGA hardware, BORPH offers a homogeneous UNIX interface for both software and hardware processes. Hardware processes inherit the same level of service from the kernel,...

This paper describes the digital complex signal processing techniques for a pulse-based UWB radio. The pro- posed baseband is essential to fully exploit the wideband signal characteristics as well as compensating the analog front-end impairments. The property and optimal usage of these signal pro- cessing blocks are analyzed for both data detection...

A flexible, low power, "mostly-digital", DC-1 GHz impulse-UWB transceiver front-end is presented. By duty-cycling nearly all of the circuitry with the pulse rate, power consumption of 570 muW (RX) and 350 muW (TX) is presented at 1 Mpulse/s with 1-bit, 1.92 GSample/s sampling, 50 Omega input matching, and 42 dB of gain at 1.1 V. Additionally, the t...

This paper describes the implementation issues of the proposed sub-sampling impulse radio architecture. By using link budget analysis and system-level simulations with measured pulse and ambient noise, the system specifications of the critical blocks are provided. From circuit implementation perspective, the most challenging block is the high-speed...

This work comprises an array of 4 phase shifters and antennas operating at 60GHz for a beamforming system. Pass gates form the switching core for a phase selector circuit which is replicated to build up a vector modulator phase shifter. The final beam accuracy is better than 2deg for a 16-way system. The die area is 2.7mm times 2.8mm, the buffers t...

In this paper we present an experimental study that comprehensively evaluates the performance of three different detection methods proposed for sensing of primary user signals in cognitive radios. For pilot and energy detection, our measurement results confirmed the theoretical expectations on sensing time performance. However, a physical implement...

Advances in FPGA-based reconfigurable computers have made them a viable computing platform for a vast variety of computation demanding areas such as bioinformatics, speech recognition, and high-end digital signal processing. The lack of common, intuitive operating system support, however, hinders their wide deployment. This paper presents BORPH, an...

The SOCRE program focused on developing a simulation engine for real-time emulation of large, complex mixed signal IC designs. The methodology utilizes the BEE2 reconfigurable computing platform with a compute capability at or near teraop/sec performance levels, allowing it to perform real-time evaluations of architectures and algorithms as well as...

Spectrum sensing has been identified as a key enabling functionality to ensure that cognitive radios would not interfere with primary users, by reliably detecting primary user signals. Recent research studied spectrum sensing using energy detection and network cooperation via modeling and simulations. However, there is a lack of experimental study...

Cognitive Radios have been advanced as a technology for the opportunistic use of under-utilized spectrum since they are able to sense the spectrum and use frequency bands if no Primary user is detected. However, the required sensitivity is very demanding since any individual radio might face a deep fade. We propose light-weight cooperation in sensi...

A methodology for VLSI realization of signal processing algorithms for wireless communications is presented that optimizes architecture for reduced power and area. When power is limited, optimal architecture represents a point on the best power-area tradeoff curve that is obtained by balancing the algorithm throughput with the power-performance tra...

In ultra-wideband (UWB) systems, antennas act as filters that introduce a frequency dependent response from the transmitter to receiver. To capture the waveform dispersion so that one can equalize/compensate at the transmitter/receiver, a new circuit modeling methodology that handles omnidirectional small antennas is proposed. By transforming the a...

The impact of scattering condition and array configuration on performances are inseparable in early analyses of multiple-antenna systems. An array-independent scattering model is introduced where three basic scattering mechanisms are modeled. Performance results become more intrinsic property of the scattering channel itself. For linear arrays of l...

A 1.2V 6b ADC using asynchronous processing with dual time interleaving and non-binary successive approximation achieves 600MS/s while dissipating 5.3mW in a 0.13mum CMOS process. A capacitive ladder network is used to reduce the input capacitance without compromising matching accuracy. The ADC occupies an active area of 0.12mm² and has...

A major shift in radio design is now just beginning which attempts to share spectrum in a fundamentally new way. These radios are addressing the fact that spectrum is actually poorly utilized in many bands, in spite of the increasing demand for wireless connectivity. The new approaches to spectrum sharing make use of the advances in technology to i...

An ASIC realization of the MIMO baseband processing for a multi-antenna WLAN is described. The chip implements a 4times4 adaptive singular value decomposition (SVD) algorithm with combined power and area minimization achieving a power efficiency of 2.1GOPS/mW in just 3.5mm² in a 90nm CMOS. The computational throughput of 70GOPS is implem...

A highly integrated, flexible, baseband impulse-UWB transceiver front-end has been implemented in a standard 0.13mum CMOS process with power consumption of 1.8mW (RX) and 0.5mW (TX) at 10 Mpulses/s with a 1.1V supply. This transceiver targets a sensor network application and comprises a 1-bit, 1.92 GSample/s A/D conversion, 50Omega input matching w...

In this paper we study the suitability of constant envelope multi-carrier modulation technique for the implementation of 1 Gbps wireless link at 60 GHz. This technique combines orthogonal frequency division multiplexing (OFDM) and phase modulation (PM) where: (1) PM creates a constant envelope signal which allows high power amplifier to operate nea...

There are a number of new radio systems which exploit novel strategies being made possible by the regulatory agencies to increase the availability of spectrum for wireless applications. Three of these that will be discussed are Ultra Wideband (UWS), 60 GHz and cognitive radios. The UWB approach attempts to share the spectrum with higher priority us...

Cognitive radio systems offer the opportunity to improve spectrum utilization by detecting unoccupied spectrum bands and adapting the transmission to those bands while avoiding the interference to primary users. This novel approach to spectrum access introduces unique functions at the physical layer: reliable detection of primary users and adaptive...

This paper presents the system architecture, modeling, and design constraints for a baseband, integrated, CMOS, impulse ultra-wideband transceiver targeting very low power consumption on the order of 1 mW. Intended for a sensor network application, the radio supports low communication rates (∼100 kpbs) and ranging capabilities over short distances...