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Citations since 2016
2 Research Items
January 2011 - April 2021
- Design consulting and Company design services for Analog/Mixed-Signal ASIC design (ADC, DAC, LDO, Amplifier) https://continiumtech.com/
January 2009 - August 2010
National Semiconductors Europe AG
- Bandpass CTSD ADC for 4G Base Stations (20MHz BP @ IF=107/170MHz, -159dBc/Hz noise density, -95dB THD/IM3)
Analog circuit technique to compensate for errors of SC circuitry due to finite gain and offset of operation amplifiers (OpAmp) in ADC (Analog-Digital Converters)
Design of high-resolution Nyquist rate A/D converter necessitates the usage of advanced circuit techniques to compensate for arising analog errors. In switched capacitor ADC, besides the well know techniques such as bottom plate sampling, mismatch-independent and redundant (RSD: 1.5bit/stage) conversion for the elimination of charge injection, capa...
Zusammenfassung Es werden Anwendungsmöglichkeiten einer analogen HDL (AHDL) in den verschiedenen Entwurfsetappen bzw.-ebenen auf Grund der Erfahrungen an einem am IMMS Erfurt praktisch ausgeführten Top-Down-Entwurfs eines zykli-schen AD-Converter (ADC) gezeigt. Diese bezie-hen sich insbesondere auf die Anwendung der Spectre-HDL (oder Verilog-A) in...
We discuss an simple approach of voltage-to-current conversion intended to provide a front-end interface for current-mode processing systems. The circuit principle is based on a high-resistive CMOS inverter followed by current-mirrors. Over the entire rail-to-rail input range an output linearity error less than 4.37% and THD of 2.253% are achieved....
This paper briefly describes a biologically inspired model for sound source localization. In the whole neural system an advanced integrate-and-fire neuron model is used for spike coding, time delay evaluation and in a Winner-Take-All (WTA) network. We discuss a current-mode CMOS synapse circuit transforming the binary action potential (AP) into an...
This paper describes a 1MHz CMOS implementation of an integrate and fire neuron network. The system models the human ability to separate unknown sounds under natural conditions. Sound sources are separated based on binaural time delay of auditory nerve spiking pattern. The acoustical attention is guided by the novelty of a sound, acquired knowledge...
This work concentrates on the special problems of developing integrated circuit (IC) solutions for neuromorphic systems. A module generator Layoutcompiler for the realization of different network size and connectivity is presented. It is based on a midified Tclk/Tk interpreter.
. This paper describes a 1MHz CMOS implementation of a neural network used for auditory attention. The system models the human ability to separate unknown sounds under natural conditions. Sound sources are separated based on interaural time delay. The acoustical attention is guided by the novelty of a sound, acquired knowledge and interaction with...
This paper describes an analog VLSI implementation of an Integrate-and-Fire neural network. The system models the human ability to localize sounds under natural conditions and based on binaural time delay corresponding to angle deflection. Acoustic signals are coded into spiking sequences modeling the response of inner hair cells and processed as c...
This paper describes a 1MHz CMOS implementation of a neural network used for auditory attention. Signals are coded into binary spikes modelling the biology. A uniform model of pulse propagating cell is used in diierent performing stages. The signal processing is distributed to neurons and synapses realized as analog circuits.
This paper describes a hardware implementation of a firing neural network based on the models of Gerstner. It mainly consists of analog building blocks (neurons, synapses), but because of their digital interface and controlling it is a mixed-mode structure. The complete physical implementation of all components allows massive parallel and real time...
We started importing EDIF from Tanner2016 to OA, to be able to design and to interchange the OA database between Tanner2019 and Cadence IC6.1.8. However the interoperability of this schematics in OA fails!
Any design schematics from CDS are fully readable and fully useable in Tanner2018 and Tanner2019. The same applies also for Layouts and Symbols from CDS into Tanner.
We see OA-interoperability problems when comming with OA-database from Tanner2018/Tanner2019 into CDS 6.1.8. Virtuoso schematic editor:
1.) invisible "ghost" wires: they physically are existing/moveable/contactable, but are not visible
2.) TannerFakeNet wires: where EDIF-Tanner used zero-length net-names directly placed on a block symbol (we corrected it in Tanner and imported anew) after Tanner2019 OA import (which was in Tanner readble) we used the OA database in CDS, but IC6.1.8. did not recognize this short stump/stub and place "TannerFakeNet" in net-wire name light-blue-color (CDS wire default color).
3.) wires carrying "Not Checked Yet" property: which leads to a behaviour, that the whole wire looses its original name (TannerOA) and when this net is connected to a pin, then it causes in CDS an error, because no-net-name wire being connected to a pin. This behaviour does not vanish in CDS when we delete all the wires and redraw the wiring anew.
3A) then we started to delete the pins to be able to overwrite the netname. This did not help, deleting pin leads to still stacking net-name "Not Checked Yet", we are not able to correct the net-name even without pin.
The most critical problem is the 3.) and 3A)
We further evaluated the behaviour of the lost net-name (Not Checked Yet).
1.) We see, that the untouched schematic in read-only mode, just after being copied directly from Tanner (Win to Linx directory copy) is initially clean. All wires are available, each wire carries its original name.
The problem starts as soon as we open the schematic in CDS in edit mode and run initial check-and-save. This immediately generates the unvisible wires and some wires looses its name (they get the "Not Checked Yet" property). Probably the intial netlisting causes that from the OA database this missing net-name is loaded to the schematic view ???
2.) We deleted sequentially all the pins in CDS schematic editor and running CDS check-and-save, to delete potential source of problems (no pin => not net-name error, and to be able later include new pins per name). When the last Pin in CDS is deleted, then first the CDS Schematic windows crashes and after 10-15 sec also the whole Cadence IC6.1.8 crashes.
3.) we ran "oascan" over the database and it was clean. Also selectively over the destroyed schematic cell. no error, no repair occurs.
4.) we see in CDS Schematic Editor that in the corruct OA-schematic from Tanner2019, each pin comming from Tanner carries 3 additional properties: .
TannerOriginalName = VEEA, TannerPortGlobal=0, Tanner PortType=6.
These 3 properties can be deleted in CDS, but the pin or the whole OA schematic is still somehow corrupted. The OA-resaving in CDS is not able to delete the problem in OA, since even pins without Tanner properties causes schematic errors. CDS never can clean the OA-format problems which occurs when saving in Tanner.
We see, that any OA database generated in CDS IC6.1.8 is readable, usable in Tanner2019. There are no problems with Layout, nor with Schematic, nor with Symbol. Thus the way CDS => Tanner is working, but the reverse was Tanner => CDS does not work for OA. Thus the OA-interoperability is not working between Tanner and CDS
___________________________________________________________________ We conclude, that there must be a problem in writing OA format or reading the OA with additional feature. But we can not conclude where the problem is located, as we are not familiar with OA standard.
Thank you very much for any comments in advance.
Continium Technology's R&D Project to develop a 100MS/s current steering DAC with 96dB SNR in 300kHz and 20b linear (DNL) and 90dB THD in 10MHz, integrated in 180nm 5V CMOS
Design of medium resolution (12-14 Bit) A/D converters (ADC) and D/A converters (DAC) based on serial conversion to co-integrate memristor neuromorphic device with its interface circuit @ µW power consumption on lowest chip area. The project is integrated within the IPCEI (important project of common european interest) initiative and will be done with our direct part BIZZCOM. 1st milestone: MPW prototype of ADC-DAC with package integration with memristor crossbar/matrix 2nd milestone: multi-channel ADC/DAC and MCU CMOS chip with ALD deposition above the BEOL and oxide passivation to generate a SoC.