Raul Perez

Raul Perez
Catalan Institute of Nanoscience and Nanotechnology | ICN2 · Nanofabrication Facility officer

PhD

About

32
Publications
13,369
Reads
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1,064
Citations
Citations since 2017
3 Research Items
778 Citations
2017201820192020202120222023020406080100120140
2017201820192020202120222023020406080100120140
2017201820192020202120222023020406080100120140
2017201820192020202120222023020406080100120140
Additional affiliations
September 2015 - December 2020
ICN2
Position
  • Senior Officer
Description
  • Senior officer of 100m2 cleanroom facility for nanofabrication.
May 2014 - present
ICFO Institute of Photonic Sciences
Position
  • Engineer
Description
  • Graphene devices
January 2013 - May 2014
IBEC Institute for Bioengineering of Catalonia
Position
  • Nanotechnology Platform technician
Education
September 2001 - October 2004
Autonomous University of Barcelona
Field of study
  • Materials Science
September 1995 - October 1999
University of Barcelona
Field of study
  • Physics

Publications

Publications (32)
Article
Full-text available
Integrated circuits based on CMOS (complementary metal-oxide semiconductors) are at the heart of the technological revolution of the past 40 years, as these have enabled compact and low cost micro-electronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible light camer...
Article
Controlling molecular interactions between bioinspired molecules can enable the development of new materials with higher complexity and innovative properties. Here we report on a dynamic system that emerges from the conformational modification of an elastin-like protein by peptide amphiphiles and with the capacity to access, and be maintained in, n...
Article
In this paper, we describe the discovery and characterization of shelled structures that occur inside galleries of Pyrenees mines. The structures are formed by the mineralization of iron and zinc oxides, dominantly franklinite (ZnFe2O4) and poorly-ordered goethite (α-FeO(OH). Subsurface oxidation and hydration of polymetallic sulfide orebodies prod...
Article
Secondary ion mass spectrometry is a technique used for surface analysis. The recent introduction of metal cluster ionization sources opened the possibility to probe biological tissues, due to its reduced in-source fragmentation. Despite its limitations in mass range of the molecules analyzed, a combination of minimal sample processing, sensibility...
Article
Full-text available
Here, we report on a comparison of two different methods to achieve thin deposited layers for gate oxide on n- and p-type GaN by using plasma-enhanced chemical vapor deposition with silane and tetraethyl orthosilicate precursors. An annealing was performed at for 2 min in ambient as an attempt to improve electrical characteristics. Before...
Article
Full-text available
Atherosclerosis is prevalent in diabetic patients, but there is little information on the localization of nonesterified fatty acids (NEFAs) within the plaque and their relationship with inflammation. We sought to characterize the NEFA composition and location in human diabetic atheroma plaques by metabolomic analysis and imaging and to address thei...
Article
As candidate materials for future thermonuclear fusion reactors, isolating ceramics will be submitted to high energy gamma and neutron radiation fluxes together with an intense particle flux. Amorphization cannot be tolerated in ceramics for fusion applications, due to the associated volume change and the deterioration of mechanical properties. The...
Article
The advent of metal cluster as a primary ion source in the late 1980s, made it feasible to probe surfaces for complex organic structures due to a reduced in-source fragmentation, and opened the door to the direct analysis of biological samples. Despite the mass range measurable by TOF-secondary ion MS (SIMS) still being rather limited, the informat...
Article
High voltage SiC semiconductor devices have been successfully fabricated and some of them are commercially available [1]. To achieve experimental breakdown voltage values as close as possible to the theoretical value, i.e. value of the theoretical semi-infinite diode, it is necessary to protect the periphery of the devices against premature breakdo...
Article
We have performed nitrogen and phosphorus co-implants at room temperature to obtain high n-type carrier concentration layers in SiC. An inductive heating RTA furnace has been used for the activation annealing. The influence of the temperature ramp parameters such as rise/decrease temperature speed and intermediate annealing steps on the dopant acti...
Article
4H–SiC metal-oxide-semiconductor capacitors have been constructed using deposited SiO2 from tetra-ethoxy-silane (TEOS) in the gate process fabrication. The effect of prior deposition interfacial “low temperature” (when compared with a standard thermal oxidation) oxidation (O2 and N2O) and SiO2-TEOS post-deposition annealings (N2, O2, N2O and Ar) ha...
Article
Full-text available
In this work we investigate the current–voltage characteristics of fabricated junction barrier Schottky (JBS) rectifiers with different aluminium implantation profiles in their p-type grid regions. Good performance characteristics of 1.2 kV JBS, Schottky and implanted PiN diodes processed on the same 4H-SiC wafer have been tested. A bilayer Ni/Ti a...
Article
Full-text available
This paper presents the design, fabrication, and comparison of different planar edge termination techniques on high-voltage 4H-SiC PiN diodes, including single- and double-junction termination extensions (JTE), floating guard rings, and a novel termination structure, the so-called "floating guard rings-assisted JTE." The influence of the anode meta...
Article
Full-text available
We report a full wafer scale investigation of the activation of nitrogen and phosphorus ions co-implanted at room temperature in a 4H-SiC semi-insulating wafer. We used a full 35 mm wafers on which, after implantation and annealing, 77 reticules with Hall bars and TLM motifs were processed. We found an average sheet resistance of 531 Ω2/square with...
Article
In this work we demonstrate performant characteristics of 1.2KV Schottky, Junction Barrier Schottky (JBS) and implanted PN diodes processed on the same 4H-SiC wafer. A bi-layer Ni/Ti scheme for the contact metallisation submitted to high temperature rapid thermal anneals is proved to form good ohmic contact on p+ implanted areas while maintaining g...
Article
We report a full wafer size investigation of the homogeneity of electrical properties in the case of co-implanted nitrogen and phosphorus ions in 4H–SiC semi-insulating wafers. To match standard industrial requirements, implantation was done at room temperature. To achieve a detailed electrical knowledge, we worked on a 35 mm wafer on which 77 diff...
Conference Paper
Full-text available
SiC Schottky barrier diodes (SBD) are commercially available in the 600 V breakdown voltage range and 1.2 kV SiC SBDs have been announced. In this paper we compare the behavior of recently fabricated high-current 1.2 kV SBD with that of equivalent Si diodes, underlining the high temperature working operation capability (up to 200 degrees C). Lower...
Article
The behaviour of Ni/Ti bilayer contacts on 4H-SiC with different thermal anneals is reported, as well as their impact on the electrical characteristics of both Schottky and PN diodes processed on the same wafer. A 350 °C rapid thermal annealing (RTA) provides the optimal forward performances of Schottky contacts with the lowest forward voltage drop...
Article
The analysis of “nonideal” behaviour in current–voltage characteristics of fabricated Schottky diodes on 4H–SiC is carried out. An accurate theoretical modelling of the effect of the presence of inhomogeneities on the electron transport across the metal-semiconductor interface is applied. This model trends to explain a large series of abnormal expe...
Conference Paper
In this work we demonstrate performant characteristics of 1.2KV Schottky, Junction Barrier Schottky (JBS) and implanted PN diodes processed on the same 4H-SiC wafer. A bi-layer Ni/Ti scheme for the contact metallisation submitted to high temperature rapid thermal anneals is proved to form good ohmic contact on p(+) implanted areas while maintaining...
Article
Full-text available
We report a comparative investigation of the activation kinetics of nitrogen and phosphorus ions implanted at room temperature in 4H-SiC semi-insulating substrates. We characterised the electrical activation through a fast non-contact method (eddy current) which gives the sheet resistance after every annealing step. The surface roughness was monito...
Article
Full-text available
Traditional junction termination extension (JTE) designs required precise control of dopant profiles in the JTE layer in order to achieve total depletion at the desired blocking voltage. To extend the JTE range of impurity concentration for obtaining high breakdown values we have optimised and developed a new termination called "guards rings assist...
Conference Paper
Surface treatment is a key technological parameter in the microelectronics technology and especially for SiC devices since high temperatures must be used for implanted impurities annealing and crystal damage recovery. In this work we take profit of a novel fine polishing process developed by NOVASIC to improve the electrical characteristics of Boro...
Article
We report on the structural and electrical properties of four different 6H-SiC samples implanted to a final concentration of 8×1019 cm-3. The implantation was done at room temperature using either N+ or P+ or (N+-P+) co-doping. In all three cases, from micro-Raman experiments, we demonstrate a good lattice recovery. From transport experiments, we f...
Article
The device structure of a 2 kV 4H–SiC P+NN+ planar diode with different edge terminations is optimised with simulation results. Since the periphery protection is a key issue in the design of Silicon carbide (SiC) power diodes, several techniques such as single- and double-junction termination extension (JTE) and a combination of JTE and guard rings...

Questions

Questions (2)
Question
Hi,
I am trying to do a liftoff processing with AZ5214E (positive) after HfOx ALD deposition at 110ºC for 40nm thickness.
I have experienced two main problems:
1. When the sample is put in the ALD system just few time after development It turns out that when the ALD process is finished I observe that the resist is shown to be "exploded" in bubbles shapes during the processing. 
2. The liftoff is quite hard to get done properly on small patterned regions (8x8um squares), even after sonication in acetone for 30min at 60ºC.
I guess that the solution for problem 1 is to do some hardbake before putting the sample into the ALD chamber. I have tried that (90ºC for 2min in a hotplate) and it has'nt worked out. I guess that so should go to higher temperatures (120ºC for 3 min?). Also i could try to leave the sample in vacuum for 24h to do some PR outgassing.
I would really appreciate some help/advise to solve these issues.
Thanks in advance.
Best,
Raúl. 
Question
Does anyone know if PR AZ1512 endures an ITO wet etching process based on diluted HNO3 and HCl? Which PR thickness would be necessary to etch 600 nm of ITO?

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