About
69
Publications
16,317
Reads
How we measure 'reads'
A 'read' is counted each time someone views a publication summary (such as the title, abstract, and list of authors), clicks on a figure, or views or downloads the full-text. Learn more
529
Citations
Introduction
Pietro Nannipieri currently works at the Department of Information Engineering, Università di Pisa. Pietro does research in Electronic Engineering, Communication Engineering and Aerospace Engineering.
Current institution
Publications
Publications (69)
Field Programmable Gate Arrays are extensively utilized across numerous domains, including telecommunications, cryptography, Machine Learning, and safety-critical applications. In critical applications, FPGAs are often exposed to environmental challenges, such as Single Event Upsets, which can affect the reliability of the design. Therefore, assess...
Field Programmable Gate Arrays find extensive use across various domains, ranging from telecommunications to Machine Learning tasks. In the context of space applications, they emerge as a highly favourable choice, owing to their high degree of flexibility and their accessibility in different silicon-grade technologies. However, due to the high asso...
This paper presents a cycle-accurate verification environment for the Crypto-Tile, a cryptographic accelerator integrated into the EPI General Purpose Processor. The focus of this work is to provide a robust methodology for validating the functionality and performance of the Crypto-Tile. The verification environment includes an in-depth examination...
Recently, there has been a growing interest in Physically Unclonable Functions (PUFs). These electronic circuits possess several key characteristics such as unpredictability and uniqueness that make them particularly attractive for security applications. PUFs offer an appealing solution for secure boot applications, providing a hardware-based mecha...
This work centres on designing and implementing a Low-Density Parity-Check (LDPC) Encoder on a Xilinx Field Programmable Gate Array (FPGA). The encoder will be part of the Digital Video Broadcasting Satellite 2nd generation (DVB-S2) Transmitter Intellectual Property (IP) for a High Data-Rate Downlink Telemetry System in the context of Earth Explora...
In the dynamic fields of semiconductor design and digital system development, effective verification procedures are in high demand. In particular, functional verification is essential for space systems to guarantee mission success, prevent errors in intricate environments, and uphold the reliability vital for effective space exploration. Testing ph...
Cyberattacks and cybercriminal activities constitute one of the biggest threats in the modern digital era, and the frequency, efficiency, and severity of attacks have grown over the years. Designers and producers of digital systems try to counteract such issues by exploiting increasingly robust and advanced security mechanisms to provide secure exe...
p>Artificial Intelligence has gained widespread adoption across different industrial sectors, serving as a versatile tool to carry out a diverse array of tasks, ranging from image classification and traffic forecasting to natural language processing and speech recognition. In the space domain, however, a special focus must be placed on area overhea...
p>Artificial Intelligence has gained widespread adoption across different industrial sectors, serving as a versatile tool to carry out a diverse array of tasks, ranging from image classification and traffic forecasting to natural language processing and speech recognition. In the space domain, however, a special focus must be placed on area overhea...
p>This work presents a highly parameterised CGRA-based accelerator that we developed for an extensive Design Space Exploration activity on design parameters. The description starts from the CGRA building blocks, the Functional Units, and progresses towards the top level of the architecture, represented by the Node component, which is composed of an...
p>This work presents a highly parameterised CGRA-based accelerator that we developed for an extensive Design Space Exploration activity on design parameters. The description starts from the CGRA building blocks, the Functional Units, and progresses towards the top level of the architecture, represented by the Node component, which is composed of an...
The on-board communication standard adopted in current generation space missions of the European Space Agency, and many other agencies as well, is SpaceWire (SpW). In a SpW network, data are exchanged as well-formed packets, whose structure offers low packet overhead and allows developers to tailor their implementation for SpW applications. The dev...
Random number generators are a key element for various applications, such as computer simulation, statistical sampling, and cryptography. They are used to generate/derive cryptographic keys and non-repeating values, e.g., for symmetric or public key cyphers. The strength of a data protection system against cyber attacks corresponds to the strength...
This work describes the hardware implementation of a cryptographic accelerators suite, named Crypto-Tile, in the framework of the European Processor Initiative (EPI) project. The EPI project traced the roadmap to develop the first family of low-power processors with the design fully made in Europe, for Big Data, supercomputers and automotive. Each...
To ensure the flexibility of Earth Observation satellite missions, it is essential to have highly adaptable communication systems equipped with efficient modulation and coding schemes. The preferred approach for such applications is the DVB-S2 standard, which provides three operational modes: Constant Coding and Modulation, Variable Coding and Modu...
Digital designs complexity has exponentially increased in the last decades. Heterogeneous Systems-on-Chip integrate many different hardware components which require a reliable and scalable verification environment. The effort to set up such environments has increased as well and plays a significant role in digital design projects, taking more than...
SpaceWire (SpW) devices are widely used in space applications on-board satellites. Their verification is fundamental because it ensures that the Design Under Test (DUT) is bug-free, without the risk of compromising an entire space mission.
In this paper an innovative architecture of a Verification Intellectual Property (VIP) based on Universal Veri...
In the cybersecurity field, the generation of random numbers is extremely important because they are employed in different applications such as the generation/derivation of cryptographic keys, nonces, and initialization vectors. The more unpredictable the random sequence, the higher its quality and the lower the probability of recovering the value...
This paper presents a System-on-Chip (SoC) implementation of a cryptographic hardware accelerator supporting multiple AES based block cypher modes, including the more advanced CMAC, CCM, GCM and XTS modes. Furthermore, the proposed design implements in hardware advanced features for AES key secure storage. A flexible interface allows the communicat...
This article presents a cryptographic hardware (HW) accelerator supporting multiple advanced encryption standard (AES)-based block cipher modes, including the more advanced cipher-based MAC (CMAC), counter with CBC-MAC (CCM), Galois counter mode (GCM), and XOR-encrypt-XOR-based tweaked-codebook mode with ciphertext stealing (XTS) modes. The propose...
In recent years, public-key cryptography and digital signature have become fundamental components of digital infrastructures. Such a scenario has to face a new and increasing threat, represented by quantum computers. It is well known that quantum computers in the next years will be able to run algorithms capable of breaking the security of currentl...
The complexity of heterogenous Systems-on-Chip has overgrown in the last decades, and the effort necessary to set up a verification workflow has increased as well. The time spent on the verification phase of a design takes on average 57% of the project time, and in these years, several solutions aimed to automate that task have been developed. Some...
Cybersecurity is a critical issue for Real-Time IoT applications since high performance and low latencies are required, along with security requirements to protect the large number of attack surfaces to which IoT devices are exposed. Elliptic Curve Cryptography (ECC) is largely adopted in an IoT context to provide security services such as key-exch...
In this chapter we will introduce the SpaceFibre standard, providing an overview of its layers. The objective of the chapter is to support the reader in the understanding of the different layers; even though the standard contains all the necessary information to build a SpaceFibre-based system, it can be difficult to be understood at first. We do n...
This chapter introduces the various building blocks of a complete SpaceFibre network, by proposing a design methodology behind each of them. We will introduce a general architecture of a SpaceFibre CoDec, focusing on the main challenges that a designer has to undertake in the development process of such a system. We will also present a bus function...
This chapter will introduce the basic concepts on the main building block of the data handling system of a spacecraft. We will introduce the main requirements which it has to withstand, also observing their evolution trends. The current operating solution in terms of on-board data-handling is illustrated, trying to focus on their strengths and weak...
This chapter is aimed at measuring the maturity of the SpaceFibre protocol specification by conducting interoperability tests between separately developed SpaceFibre implementations. On the one hand, such tests can significantly contribute to the hardware validation efforts of every single interface. On the other hand, they also validate the correc...
In this chapter, we will survey all the existing SpaceFibre-based products. First, we will give an overview of the state-of-the-art FPGA technology in the space domain able to host a SpaceFibre interface. We will then present and compare the available solution for SpaceFibre CoDecs, routing switches and Electrical Ground Segment Equipment. We aim t...
In this chapter, we will focus on the SpaceFibre Network layer. In particular, we will try to reproduce the approach that a system engineer would have in the design of a complex SpaceFibre network, providing the necessary tools and references. The first step consists of performing a high-level simulation of the network to verify if it has been desi...
Random numbers are widely employed in cryptography and security applications. If the generation process is weak, the whole chain of security can be compromised: these weaknesses could be exploited by an attacker to retrieve the information, breaking even the most robust implementation of a cipher. Due to their intrinsic close relationship with anal...
On-board data handling sub-systems shall provide robust communication on-board spacecraft and have strict requirements in terms of reliability, fault-tolerance and redundancy. In the next years, on-board data handling sub-systems will be required to sustain high-speed payloads since satellites will host new high-resolution instruments, requiring a...
This book introduces the space community to the novel SpaceFibre protocol, developed under the guidance of the European Space Agency (ESA) as the forthcoming, high speed (Gbps) communication protocol for satellite on-board communication. Since SpaceFibre is expected to follow the success of its predecessor SpaceWire protocol (Mbps), the authors pro...
This paper proposes the architecture of the hash accelerator, developed in the framework of the European Processor Initiative. The proposed circuit supports all the SHA2 and SHA-3 operative modes and is to be one of the hardware cryptographic accelerators within the crypto-tile of the European Processor Initiative. The accelerator has been verified...
SpaceFibre is a high-speed satellite on-board communication protocol. It allows high data rates (up to 6.25 Gbps per lane), advanced quality of service, fault detection isolation and recovery. Different SpaceFibre nodes can be combined, together with a SpaceFibre routing switch, to form a network. This work aims to describe the set-up of a SpaceFib...
In the last few years, satellite on-board data handling bandwidth requirements grew significantly, as well as production volume of these systems. A series of different protocols currently try to answer this need. In particular, the European Space Agency developed an open protocol solution: SpaceFibre. The SpaceFibre protocol can sustain a line rate...
Nowadays, requirements for satellite electronics are becoming more stringent due to the increasing complexity of space missions. In particular, data rate requirement is growing up due to the adoption of high-speed payloads such as Synthetic Aperture Radars and hyper-spectral imagers that overcome the capability of state-of-the-art on-board data han...
The Advanced Microcontroller Bus Architecture Advanced eXtensible Interface is a memory mapped protocol intended for internal System on Chip communications. However, there is no mean to directly exchange data between AXI devices and LabVIEW applications. This work proposes a novel and streamlined bridge solution to transfer data directly and effect...
In the last few years, data rate requirement in on-board data handling for space missions has continuously grown, due to the presence of high resolution instruments. This lead the European Space Agency to start working on a new communication standard named SpaceFibre. It is able to fulfil a data rate of 6.25 Gbit/s per communication lane (up to 16...
This article presents a complete test equipment for the promising on-board serial high-speed SpaceFibre protocol, published by the European Committee for Space Standardization. SpaceFibre and SpaceWire are standard communication protocols for the latest technology sensor devices intended for on-board satellites and spacecrafts in general, especiall...
SpaceFibre is an upcoming on-board high-speed communication protocol for space applications. It has been developed in collaboration with the European Space Agency to answer the growing data-rate requirement of satellite payloads such as Synthetic Aperture Radars or hyper-spectral imagers. SpaceFibre offers a complete set of features (i.e., Fault De...
In this paper, the development and implementation of the clustering algorithm (CA) developed for an instrument to detect lightning phenomena (Lightning Imager) is presented. The aim of the Lightning Imager (LI) instrument is to provide information relevant to the localization and the radiance of lightning events with respect to terrestrial systems....
This paper introduces a comprehensive test equipment for early adopters of the new ECSS satellite on-board serial high-speed communication protocol, SpaceFibre, maintaining also retro-compatibility with its precursor, SpaceWire. The presented system is based on the PCI eXtension for Instrumentation (PXI) industry standard and designed with cutting...
In the last few years, satellite on board data handling data rate requirements increased dramatically, from hundreds of megabits per second to several gigabits per second. SpaceWire, the current generation European standard communication protocol, is no more able to satisfy the demanding requirements, while the upcoming protocol, SpaceFibre, has no...
The technology advancement of satellite instruments requires increasingly fast interconnection technologies, for which no standardised solution exists. SpaceFibre is the forthcoming protocol promising to overcome the limitation of its predecessor SpaceWire, offering data-rate higher than 1Gbps. However, while several implementations of the SpaceFib...
Data rate requirements, from consumer application to automotive and aerospace grew rapidly in the last years. This led to the development of a series of communication protocols (i.e. Ethernet, PCI-Express, RapidIO and SpaceFibre), which use more than one communication lane, both to speed up data rate and to increase link reliability. Some of these...
The continuous innovation of satellite payloads is leading to an increasing demand of data-rate for on-board satellite networks. In particular, modern optical detectors generate and need to transfer data at more than 1 Gbps, a speed that cannot be satisfied with standardized technologies such as SpaceWire. To fill this gap, the European Space Agenc...
In the last few years, data rate requirement on on-board satellite communication systems significantly grown. The need of high speed networks led to the birth of the SpaceFibre protocol, which is able to run at several Gigabit per second and operates over both optical fibre and copper cables. A key feature of SpaceFibre is the possibility to have m...
8B/10B is an encoding technique largely used in different communication protocols, with several advantages such as zero DC bias. In the last years transmission rates have grown rapidly, thus the need of encoders with better performance in terms of throughput, area and power consumption raised rapidly. In this article we will present and discuss the...
U-PHOS Project aims at analysing and characterising the behaviour of a large diameter Pulsating Heat Pipe (PHP) on board REXUS 22 sounding rocket. A PHP is a passive thermal control device where the heat is efficiently transported by means of the self-sustained oscillatory fluid motion driven by the phase change phenomena. Since, in milli-gravity c...
Two Closed Loop Pulsating Heat Pipes (CLPHPs) are tested on board REXUS 18 sounding rocket in order to obtain data over a relatively long microgravity period (approximately 90 s). The CLPHPs are partially filled with FC-72 and have, respectively, an inner tube diameter larger (3 mm) and slightly smaller (1.6 mm) than the critical diameter evaluated...