Philippe Millet

Philippe Millet
NEXTER Group | NEXTER · Digital

PhD

About

34
Publications
2,821
Reads
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141
Citations
Introduction
Head of the Innovation Hub of the Digital Unit of Excellence at Nexter. His main activities focus on real-time architectures, in hardware and software, including Embedded Artificial Intelligence Accelerators for Artificial Neural Networks.
Additional affiliations
June 2020 - present
Nexter
Position
  • Head of Department
January 2016 - May 2020
Thales Group
Position
  • Innovation Leader
January 2015 - December 2015
Thales Group
Position
  • Head of Department
Education
September 1997 - November 2005
Université Paris-Sud 11
Field of study
  • Computer Science

Publications

Publications (34)
Chapter
Satellite imagery is the most important sector of space industry, as around 38% of satellites are fully dedicated to earth observation. Then, for each sample, the error gradient is propagated backward in the network, and the weights are adjusted to minimise this error. However, the bandwidth between the satellite and its ground control centre is ve...
Chapter
The development of power-efficient solutions gives new embedded products the ability to analyse images and thereby brings more intelligence to embedded systems—providing more and better services of higher quality as well as advanced capabilities such as self-adaptation and autonomy. This will allow cars to drive safer, medical devices to assist sur...
Chapter
Embedded image processing systems face stringent and conflicting constraints which commonly result in developers overly specialising systems to the problem-at-hand. In other words, they give priority to efficiency, which is an immediate concern, over the longer term development cost reduction benefits of building reusable components. In this paper,...
Chapter
Real-time X-ray imaging is used in operation theatre and induces both the patient and the staff radiation doses that might affect their health. Yet, reducing the emission of radiation means increasing the noise on the sensor signal. To restore the image quality, a dedicated processing can be established, requiring however a powerful computing unit...
Book
This book summarizes the key scientific outcomes of the Horizon 2020 research project TULIPP: Towards Ubiquitous Low-power Image Processing Platforms. The main focus lies on the development of high-performance, energy-efficient embedded systems for the growing range of increasingly complex image processing applications. The holistic TULIPP approach...
Chapter
Today, many industrial domains rely on vision-based embedded systems. High computing performance of the embedded platform is a mandatory feature for modern image processing applications. Yet, these embedded systems have to comply with strict requirements regarding size, weight and energy efficiency. Tulipp will develop a reference platform, which d...
Article
This paper describes a methodology to improve the energy efficiency of high‐performance multiprocessor architectures with dynamic and partial reconfiguration (DPR), based on a thorough application study in the field of smart camera technology. Field‐programmable gate arrays are increasingly being used in cameras owing to their suitability for real‐...
Conference Paper
Increasing the capture volume of visible cameras while maintaining high image resolutions, low power consumption and standard video-frame rate operation is of utmost importance for hand-free night vision goggles or embedded surveillance systems. Since such imaging systems require to operate at high aperture, their optical design has become more com...
Patent
L'invention concerne un procédé de détermination par optimisation d'une architecture multi-cœurs et d'une façon d'implémenter une application sur l'architecture pour une application donnée, le procédé comprend : - la fourniture d'une application parallélisée et d'architectures candidates comprenant différents blocs matériels, - la définition d'un p...
Article
This paper proposes a hardware memory management unit to implement an on-chip message passing protocol for cluster based multi-processors system on chip architectures. Within the architecture each cluster is composed of general purpose processors or digital signal processors, along with a memory. To maintain the coherence of the memory a hardware m...
Conference Paper
The deployment of an application onto a multicore archi- tecture is often a long and difficult process. This is due to the fact that the characteristics of both the architecture and the application are taken into account late in the development process. It's therefore necessary to have tools pruning the solution space efficiently and accurately. In...
Conference Paper
This paper introduces the FlexTiles platform, which consist of a manycore architecture associated with a complete tool flow. The different components of the manycore architecture are based on general purpose processors (GPP), low power DSP cores and an eFPGA on which dedicated IPs can be dynamically configured at run-time. Thus, in order to mask th...
Conference Paper
This paper introduces adaptive techniques targeted for heterogeneous manycore architectures and introduces the FlexTiles platform, which consists of general purpose processors with some dedicated accelerators. The different components are based on low power DSP cores and an eFPGA on which dedicated IPs can be dynamically configured at run-time. The...
Article
We present the FP7 project FlexTiles which main objective is to develop a heterogeneous manycore with self adaptive capabilities.
Chapter
The exponential increase of CMOS circuit complexity has opened the way to the introduction of new capabilities and functionalities into electronic systems that have been sources of innovations in major growth markets. To pursue this trend all along the last decades, major evolutions of design methodologies and ­computing architectures have been nec...
Article
Full-text available
Reconfigurable computing offers a wide range of low cost and efficient solutions for embedded systems. The proper choice of the reconfigurable device, the granularity of its processing elements and its memory architecture highly depend on the type of application and their data flow. Existing solutions either offer fine grain FPGAs, which rely on a...
Conference Paper
Full-text available
— The exponential increase of CMOS circuit complexity along the last decades has lead to two growing problems. The increasing Non-recurring Engineering (NRE) costs of ASICs or System-on-Chips are becoming only affordable to the highest volume applications. Additionally the design methodologies have not kept pace with the rising complexity leading t...
Chapter
This chapter is related to the paper “System Level Design for Embedded Reconfigurable Systems using MORPHEUS platform” (Brelet et al. (2010) System level design for embedded reconfigurable systems using MORPHEUS platform). It presents a novel approach for designing embedded reconfigurable systems. Reconfigurable systems bring a significant importan...
Chapter
The obvious complexity of a heterogeneous architecture like MORPHEUS is hidden to application designers thanks to an integrated set of tools. Deploying an application is as easy as writing C code, and assembling IPs.
Chapter
The MORPHEUS architecture principle, plus its associate toolset, bring together a significant advantage for embedded system designs: performance, flexibility and productivity. The project also prepares, to a certain extent, the future utilization of reconfigurable technologies complementarily to multi/many-core solutions.
Conference Paper
Full-text available
Reconfigurable architectures and NoC (Network-on-Chip) have introduced new research directions for technology and flexibility issues, which have been largely investigated in the last decades. Exploiting run-time adaptivity opens a new area of research by considering dynamic reconfiguration. In this paper, we present the architecture and associated...
Conference Paper
Full-text available
This paper describes the architecture of the fourth version of the evolutionary virtual agent (EVA). This new light-weight java-based implementation is based on a dynamical rule-based subsumption architecture, an XML knowledge base and a scheme kernel for scripting behavior rules. Using this architecture, the agent is able to answer questions in na...
Chapter
This article presents a software routing algorithm used to increase fault tolerance of a large-scale MIMD computer based on an isochronous crossbar network. The routing algorithm is completed with a placement algorithm that uses an evolutionary approach that allows dynamic reconfigurations of the task-processor mapping when a fault is detected.
Conference Paper
This study tries to find a new task mapping using available resources of a partially broken MIMD machine based on an isochronous crossbar network. In this framework, we compare a genetic algorithm, a genetic programming algorithm and a simulated annealing algorithm. We show evidences that both genetic algorithms seem to be excellent to solve the p...

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Projects

Projects (6)
Archived project