Péter Szántó

Péter Szántó
Budapest University of Technology and Economics · Department of Measurement and Information Systems

About

17
Publications
4,546
Reads
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15
Citations
Citations since 2017
3 Research Items
10 Citations
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20172018201920202021202220230.00.51.01.52.0
20172018201920202021202220230.00.51.01.52.0

Publications

Publications (17)
Article
Full-text available
Median filtering is a widely used non-linear noise-filtering algorithm, which can efficiently remove salt and pepper noise while it preserves the edges of the objects. Unlike linear filters, which use multiply-and-accumulate operation, median filter sorts the input elements and selects the median of them. This makes it computationally more intensiv...
Conference Paper
Full-text available
This paper describes an implementation of the Precision Time Protocol IEEE TM 1588-2002 and IEEE TM 1588-2008 in order to reach maximum accuracy in time synchronization as a requirement forsimultaneous analog data sampling. Exact cross-correlation calculation between various measurements calls for a very small phase error margin between the sampled...
Patent
Full-text available
A rank order filter and instantiation thereof in programmable logic is described. A maximum filter core frequency is determined for an input sampling frequency, a filter window height, and a number of input samples. The maximum filter core frequency is greater than the sampling frequency. The maximum filter core frequency may be insufficient for a...
Article
Full-text available
This paper presents an FPGA implementation of a high performance rank filter for video and image processing. The architecture exploits the features of current FPGAs and offers tradeoff between complexity and clock speed. By maximizing the operating frequency the complexity of the filter structure can be considerably reduced compared to previous 2D...
Article
Full-text available
Complex three dimensional graphics rendering is computationally very intensive process, so even the newest microprocessors cannot handle more complicated scenes in real time. Therefore to produce realistic rendering, hardware solutions are required. This paper discusses an FPGA implementation which supports programmable pixel computing.
Article
Full-text available
This paper presents an FPGA implementation of a high-performance rank filter for video and image processing. The architecture exploits the features of current FPGAs and offers tradeoffs between complexity and performance. By maximizing the operating frequency, the complexity of the filter structure can be considerably reduced compared to previous 2...
Conference Paper
Full-text available
There are two factors determining the performance a 3D accelerator can achieve: the available computational power and the available memory bandwidth. In embedded systems, these resources are even more limited then in desktop environments, thus the efficiency of the hardware architecture and the exploitation of the logic resources become even more i...
Conference Paper
Full-text available
Complex three dimensional graphics rendering is computationally very intensive process, so even the newest microprocessors cannot handle more complicated scenes in real time. Therefore to produce realistic rendering, hardware solutions are required. This paper discusses an FPGA implementation which complies with the newer, programmable standards. A...
Article
Full-text available
This paper presents an FIR filter architecture suitable for embedded FPGA based applications. With the limited resource requirements and its high performance, the architecture is suitable to implement real time, multi-channel filtering structures even in smaller FPGAs.
Article
Full-text available
Modeling the light-surface interaction in real time 3D applications becomes more and more complex, as users require more lifelike images. Segmented screen rendering offers a viable solution to minimize the unnecessary work done in traditional rendering architectures. However, increasing the efficiency of the rendering pipeline also increases the re...
Article
Full-text available
Segmented Screen Rendering (or Bucket Rendering) technique can considerably improve performance and/or lower external memory bandwidth requirements by segmenting the screen into small rectangles, and rendering these rectangles independently. Since the size of the buffers for a segment is significantly reduced compared to the full-screen buffers, it...
Article
Full-text available
The aim of virtual screening is to find compounds in libraries which exhibit the required properties. These properties are represented in fingerprints; during the screening process the descriptors of the compounds are compared to each other and a dissimilarity score is calculated. As compound libraries typically contain a large amount of fingerprin...

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