Paul D Franzon

• PhD
• Professor at North Carolina State University

In this work, we present empirical results regarding the feasibility of using offline large language models (LLMs) in the context of electronic design automation (EDA). The goal is to investigate and evaluate a contemporary language model's (Llama-2-7B) ability to function as a microelectronic Q & A expert as well as its reasoning, and generation c...

In this paper, we introduce Dreamweaver, which belongs to a new class of auto-regressive decision-making models known as large reasoning models (LRMs). Dreamweaver is designed to improve 3D floorplanning in electronic design automation (EDA) via an architecture that melds advancements in sequence-to-sequence reinforcement learning algorithms. A sig...

Thermal fatigue life analysis of GaN packages is an important consideration that affects the reliability and durability of electronic devices. In this paper, the fatigue life assessment of a GaN laterally conducting power packaging, including SAC305 and Sn63/Pb37 solders was conducted using the finite element analysis (FEA) method. The thermal cycl...

Thermal reliability is a critical factor in ensuring the performance and efficiency of GaN-based electronic devices. In this paper, the fatigue life assessment of a laterally conducting GaN power package that uses a two-solder hierarchy of SAC305 and Sn63/Pb37 on a 120μm thick dielectric for device attach was conducted using an FEA. The double-side...

We describe a design and fabrication experiment that has been performed to investigate a methodology for assessing the security of application specific integrated circuits (ASICs) fabricated in a split-manufacturing process based on 3-D integrated circuit (3DIC) technologies. The purpose of this process is to protect critical IP from reverse engine...

The number of design rules is drastically increasing as technology nodes scale down. This increase makes the creation of the design rule decks and the checking process complex and time-consuming. This work presents a design rule checking approach using deep learning. The core of the work consists of a framework to generate convolutional neural netw...

Hierarchical temporal memory (HTM) is an un-supervised machine learning algorithm that can learn both spatial and temporal information of input. It has been successfully applied to multiple areas. In this paper, we propose a multi-level hierarchical ASIC implementation of HTM, referred to as processor core, to support both spatial and temporal pool...

This article describes a scalable, configurable and cluster-based hierarchical hardware accelerator through custom hardware architecture for Sparsey, a cortical learning algorithm. Sparsey is inspired by the operation of the human cortex and uses a Sparse Distributed Representation to enable unsupervised learning and inference in the same algorithm...

This paper presents a compact and largely digital UHF EPC Gen2-compatible RFID implemented using digital IP blocks that are easily portable. This is the first demonstration of a digital Gen2-compatible RFID tag chip with an area of 125μm×245μm and -2 dBm sensitivity operating in the 860-960MHz band. It is enabled by a) largely standard cell-based d...

Design rule checking (DRC) is getting increasingly complex in advanced nodes technologies. It would be highly desirable to have a fast interactive DRC engine that could be used during layout. In this work, we establish the proof of feasibility for such an engine. The proposed model consists of a convolutional neural network (CNN) trained to detect...

This fourth volume of the landmark handbook focuses on the design, testing, and thermal management of 3D-integrated circuits: matching application requirements to technology-feasible implementations under electrical constraints. Edited and authored by key contributors from top research institutions and high-tech companies, the first part of the boo...

This chapter presents a comprehensive study of the unique thermal behavior in monolithic 3D‐ICs. In particular, the impact of the thin interlayer dielectric (ILD) between the device tiers on vertical thermal coupling is studied. In addition, a fast and accurate compact full‐chip thermal analysis model based on nonlinear regression technique is deve...

In order to obtain acceptable compound stack yields for 2.5D‐ and 3D‐stacked integrated circuits (SICs), there is a need to test the constituting dies before stacking. The non‐bottom dies of these stacks have their functional access exclusively through large arrays of fine‐pitch micro‐bumps, which are too dense for conventional probe technology. A...

This chapter overviews the electronic properties of a power delivery network (PDN) of integrated circuit (IC) chips, involving interactions with packages and printed circuit boards associated with system‐level assembly. The closer looks are provided for frequency‐domain impedance of a PDN with resonating peaks and how they are altered mainly by int...

This chapter presents the dynamic random‐access memory (DRAM) technology background and the 3D‐DRAM design space. It includes the evolution of DRAM technologies and interfaces and describes the common DRAM architecture and usage. The chapter highlights the large design space and shows an architecture study of a 22 nm 3D‐DRAM. It presents experiment...

TSMC has developed the Chip‐on‐Wafer‐on‐Substrate (CoWoS®) process as a design paradigm to assemble silicon interposer‐based 3D‐ICs. To reach quality requirements for volume production, several test challenges related to 3D‐ICs need to be addressed. This chapter describes the test and diagnosis solutions for the challenges that were faced in design...

Today through‐silicon via (TSV) is a mature process technology option for manufacturing of 3D stacked integrated circuits (3D‐SIC). This chapter shows the results of the system‐level/process technology co‐design analysis. It presents a design flow for carrying out exploration of 2D and 3D‐SIC implementations. The chapter considers multiple variatio...

Chip on Wafer on Substrate (CoWoS) is an interposer‐based solution to bridge the gap between the traditional 2D design and the true 3D design. It offers a massive interconnect network between the dies and the substrate. 3D‐Integrated Circuit (IC) provides several design opportunities along with the design challenges due to the scope of the system t...

3D stacked electronics presents significant challenges for heat removal due to their increased heat generation per chip footprint area over 2D architectures, power nonuniformities, and the presence of multiple interfaces within the stack. Advanced cooling designs that may address some of these thermal challenges have been investigated, including ac...

This chapter presents a method for robust optimization of 3D test architecture and test scheduling in the presence of input parameter variations. It lists examples of uncertainties in input parameters for 3D test architecture optimization and test scheduling. The chapter then formulates an integer linear programming (ILP) model for robust optimizat...

This chapter first introduces different modeling techniques with varying flexibility and complexity to be used at different stages of the design flow, ranging from fast‐solving compact thermal models for the evaluation of technology and design options, over package‐level finite element solutions, to full‐chip layout‐based thermal simulations for th...

3D‐IC and interposer technologies have demonstrated their capability to reduce system size and weight, improve performance, reduce power consumption, and even improve cost as compared with baseline 2D integration approaches. This chapter provides an overview of product and design scenarios that uniquely leverage 3D‐IC technologies in 3D specific wa...

Chip‐to‐chip interconnects can be effectively tested for stuck‐at faults and hard bridging faults via the boundary scan test standard. However, such a traditional test method may not be adequate for 3D‐ICs, in which die‐to‐die interconnects could operate at a very high speed with an end‐to‐end delay of only a few hundreds of picoseconds. Parametric...

Three dimensional integrated circuit (3D‐IC) and interposer technologies require modified computer aided design (CAD) flows. Issues that arise that are unique to 3D‐IC include evaluating the greater options afforded (pathfinding or design planning); vertical partitioning; design across a 3D stack, including placement, routing, and clock insertion;...

Advanced packaging technologies open new perspectives for system designers. Differences between the material properties can cause mechanical and electrical issues. Fan‐in/fan‐out wafer‐level packaging technologies (e.g. eWLB) and 2.5D/3D integration (e.g. die stacking) as well as the combination of traditional system integration techniques (e.g. fl...

This chapter presents various novel heat removal approaches to compile a roadmap toward true 3D integration. A topology change from single side to dual side and volumetric heat removal is a more disruptive option to reduce the thermal constraints on 3D chip stacks. Designing a thermal underfill is a multivariable problem with targets for mechanical...

Heat removal and thermal isolation are two distinct challenges facing heterogeneous 3D‐ and 2.5D‐ICs. This chapter summarizes the thermal challenges in heterogeneous three‐dimensional (3D) and 2.5D die integration architectures. To solve these challenges, interposer‐ and tier‐embedded microfluidic cooling technologies are proposed in conjunction wi...

IMEC and Cadence have jointly developed a 3D design‐for‐test (DfT) architecture that serves both 2.5D and 3D stacked integrated circuits (SICs). The architecture originally targeted stacks of monolithic, non‐hierarchical, logic‐only dies. A 3D‐DfT demonstrator circuit was designed, manufactured, and tested as part of an IMEC 3D chip stack nicknamed...

This chapter discusses cost modeling for 2.5D/3D‐stacked integrated circuits (2.5D/3D‐SICs) and presents a tool that considers all costs involved in the whole production chain, including design, manufacturing, test, packaging, and logistics. The tool provides the estimated overall cost for 2.5D/3D‐SICs and its cost breakdown for a given input param...

IEEE Std P1838 is striving to implement a flexible architecture, allowing access to die‐level DfT structures embedded within a stack of die. Access to these structures should be available at the die level, through all levels of manufacturing as each die is stacked upon the next, and finally at the package level.

This fourth volume of the landmark handbook focuses on the design, testing, and thermal management of 3D-integrated circuits, both from a technological and materials science perspective. Edited and authored by key contributors from top research institutions and high-tech companies, the first part of the book provides an overview of the latest devel...

In this paper, we present 3-D-DATE, a circuit-level dynamic random access memory (DRAM) area, timing, and energy model that models both the front and back end of 3-D integrated DRAM designs from 90-16 nm, across a broader range of emerging transistor devices and through-silicon vias. This paper improves upon previous studies by providing detailed p...

Non-traditional processing schemes continue to grow in popularity as a means to achieve high performance with greater energy-efficiency. Data-centric processing is one such scheme that targets functional-specialization and memory bandwidth limitations, opening up small processors to wide memory IO. These functional-specific accelerators prove to be...

In this work, we report on mimicking the synaptic forgetting process using the volatile mem-capacitive effect of a resistive random access memory (RRAM). TiO2 dielectric, which is known to show volatile memory operations due to migration of inherent oxygen vacancies, was used to achieve the volatile mem-capacitive effect. By placing the volatile RR...

This study presents an appliance identification algorithm for use with a non-intrusive home energy monitor based on a cogent confabulation neural network. As a cogent confabulation neural network does not require multiplications during the identification phase, it is an effective choice for systems with low-computational capability. A non-intrusive...

Reducing circuit design cost and eliminating over-design margin are the two challenges for advancing the Internet of Things (IoT). An RF-dc rectifier and storage capacitors consume 25% or more of the chip area for cost-sensitive power-harvesting-enabled IoT applications. In this paper, we explore a new circuit structure called RF-only logic that pe...

The authors of [1] would like to note the following corrections in reference numbering. It is difficult to find correct references in the currently published paper due to the reference discords.

As higher density of interconnects and packages is demanded, crosstalk noise is becoming more important. Multimode or modal signaling offers the ability to improve wiring density with significantly reduced crosstalk by coding the signals using fundamental modes of propagation only. Past work has demonstrated this on uniform channels. This paper pre...

AC-DC rectifier and storage capacitors take up 25% or more of chip area for cost-sensitive passive RFID tags. In this work, we show that these components can be eliminated by utilizing a RF-only circuit structure. Therefore, the chip would be smaller and cheaper. RF-only logic permits digital operations to be performed from an AC, rather than DC, p...

Thermal management and planning is important for heterogeneous integration due to the introduction of a complex thermal path. Thermal measurement of operating devices provides necessary data points for future design as well as validation of models. In this paper, two methods for measuring thermal performance of DAHI (Diverse Accessible Heterogeneou...

Integration of materials such as GaN, InP, SiGe, and Si is a natural extension of the 3D-IC perspective and provides a unique solution for high performance circuits. In this approach, application of a component is no longer dependent on semiconductor material selection. In this paper, preliminary results are presented which examine the thermal perf...

The stress impact of the CMOS and III–V heterogeneous integration environment on device electrical performance is being characterized. Measurements from a partial heterogeneous integration fabrication run will be presented to provide insight into how the backside source vias, alternatively referred to as through-silicon-carbide vias (TSCVs), used w...

This article consists of a single slide from the authors' conference presentation. Single-ISA Heterogeneous Multi-core: General purpose cores with different microarchitectures, tuned for different energy/performance points. Performance and energy of a program can be optimized by migrating among the core types as program characteristics change. Prio...

3DIC technology refers to stacking and interconnecting chips and substrates (“interposers”) with Through Silicon Vias (TSVs). Industry is gearing up for widespread introduction of this technology with the 22 nm node. We have been pursuing a range of approaches to enable low power computing. As well as 3DIC these include heterogeneous computing, pow...

A generally applicable calibration technique for digitally reconfigurable self-healing radio frequency integrated circuits based on a hybrid of the Nelder-Mead and Hooke-Jeeves direct search algorithms is presented. The proposed algorithm is applied to the multiobjective problem of gain error and phase error minimization for a self-healing phase ro...

A multi-capacitor coupled signaling structure is employed to enable low-power high frequency communications in 10 mm long interposer traces. On-chip Metal-Insulator-Metal (MIM) capacitor was used to implement the Multi capacitor structure. A continuous time feed forward tunable capacitive equalization was used to compensate for the frequency depend...

We studied the impedance characteristics of through-silicon via (TSV)-based power delivery networks (PDNs) for hierarchical on-die simulation and interconnect noise analysis. This paper compares the quality of power delivery in 3-D stacking scenarios for three distinct chip stacking topologies: 1) face-to-back (F2B); 2) face-to-face (F2F); and 3) b...

A memory device includes a stack of circuit layers, each circuit layer having formed thereon a memory circuit configured to store data and a redundant resources circuit configured to provide redundant circuitry to correct defective circuitry on at least one memory circuit formed on at least one layer in the stack. The redundant resources circuit in...

One challenge in computing systems is the need for new memory technologies that can improve overall performance. The development of an electrically accessible nonvolatile memory with high speed, high density, and high endurance, referred to as "Storage Class Memory" or SCM, would initiate a revolution in computer architecture. Storage class memory...

This paper describes a scalable hardware accelerator for speech recognition, which uses a two pass decoding algorithm with word dependent N-best Viterbi Beam Search. The observation probability calculation (Senone scoring) and first pass of decoding using a Bigram language model is implemented in hardware. The word lattice output from the first pas...

The DAPRA Diverse Accessible Heterogeneous Integration (DAHI) initiative seeks to build capability in production of integrated semiconductor circuits of differing materials. Integration of materials such as GaN, InP, SiGe, and Si is a natural extension of the 3D-IC perspective and provides a unique solution for high performance circuits. In this ap...

This paper describes a 3D computer architecture designed to achieve the lowest possible power consumption for “embedded applications” like radar and signal processing. It introduces several unique concepts including a low-power SIMD tile, low-power 3D memories, and 3D and 2.5D interconnect that is circuit switched so it can be tuned at run-time for...

Modern high-performance designs require accurate on-chip timing uncertainty measurements for post-silicon validation of high speed interfaces and clock distribution networks. On-chip timing measurements capabilities must keep up with growing design complexity and process variations to meet competitive product time-to-market. However, enhancing sili...

In this paper, we present novel techniques to handle the complexity and challenges in clock distribution for 3-D integrated circuit. First, we propose a novel active deskew technique to adaptively mitigate the cross-tier variations and the 3-D wiring asymmetry. The new deskew technique neither relies on an accurate through-silicon-vias model nor an...

This paper describes the modeling, fabrication, and measurement of a method to construct true 3-D antennas for radio frequency (RF) power harvesting in millimeter-scale sensors. The goal is to create an omnidirectional RF power-harvesting structure, which can provide power even if the sensor and external power source are not perfectly aligned. Beca...

Modern integrated circuit designers must deal with complex design and simulation problems while coping with large device to device parametric variations and often imperfect information. This chapter presents surrogate model-based methods to generate circuit performance models for design, device models, and high-speed input-output (IO) buffer macrom...

System architects traditionally use high-level models of component blocks to predict trends for various design metrics. However, with continually increasing design complexity and a confusing array of manufacturing choices, system-level design decisions cannot be made without considering physical-level details. This effect is more pronounced for 3-D...

Three dimensional integration technologies offer significant potential to improve performance, performance per unit power and integration density. However, increased power density and thermal resistances leading to higher on-chip temperature is imposing several implementation challenges and restricting widespread adaptation of this technology. This...

Dual floating gate flash memory has been fabricated and characterized to show dynamic operation, non-volatile operation, and simultaneous dynamic and non-volatile operation. The gate stack consists of a thin dielectric separating two floating gates sandwiched between a tunnel dielectric and interpoly dielectric. The quality of the thin dielectric t...

3D technologies offer significant potential to improve raw performance and performance per unit power. After exploiting TSV technologies for cost reduction and increasing memory bandwidth, the next frontier is to create more sophisticated solutions that promise further increases in power/performance beyond those attributable to memory interfaces al...

Single-ISA heterogeneous multi-core processors are comprised of multiple core types that are functionally equivalent but microarchitecturally diverse. This paradigm has gained a lot of attention as a way to optimize performance and energy. As the instruction-level behavior of the currently executing program varies, it is migrated to the most effici...

This paper presents a bus structure, synchronization and test scheme for fast data transfer between logic dies in stacked 3D ICs using face-to-face (F2F) micro-bumps. The proposed design permits different designs, such as microprocessor, co-processor and accelerator, to be integrated together vertically with high bandwidth and low power, which is u...

3DIC technology allows implementation of fast and dense memory by allowing multiple layers of DRAM to be fabricated in a single die called Die-stacking technology. This creates opportunity to explore usage of DRAM as fast last level cache by exploiting mapping of data and tag in the same bank. This Paper investigates the implementation of such a ca...