Patrick Adde

Patrick Adde
Institut Mines-Télécom | telecom-sudparis.eu · Département Électronique

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62
Publications
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579
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Publications

Publications (62)
Article
High throughput telecommunication systems such as long-haul optical transmission or passive optical networks require powerful error correcting codes in order to increase their optical budget. In such speed-constrained applications, the classical (255,239) Reed–Solomon code is gradually being replaced by more powerful forward error correction (FEC)...
Conference Paper
The (24, 12, 8) extended binary Golay code is a well-known rate-1/2 short block-length linear error-correcting code with remarkable properties. This paper investigates the design of an efficient low-complexity soft-decision decoding architecture for this code. A dedicated algorithm is introduced that takes advantage of the code's properties to simp...
Article
Full-text available
Maximum likelihood soft-decision decoding of linear block codes is addressed in this correspondence. A novel algorithm based on Chase-2 algorithm for the decoding of systematic binary block codes is detailed. A double re-encoding technique in place of the classical algebraic decoding for the computation of the candidate codeword list is the major i...
Article
Full-text available
This article proposes to explore parallelism in Turbo-Product Code (TPC) decoding through a parallelism level classification and characterization. From this design space exploration, an innovative TPC decoder architecture without any interleaving resource is presented. This architecture includes a fully-parallel SISO decoder capable of processing n...
Article
Full-text available
Presented is a soft-decision decoding algorithm for a particular class of rate-1/2 systematic linear block codes. The proposed algorithm performs successive re-encoding of both the data and parity bits, to produce a list of codewords among which the most likely candidate is chosen. Simulation results show that close to optimal performance can be ob...
Conference Paper
Full-text available
Cortex codes are a family of rate-1/2 self-dual systematic linear block codes with good distance properties. This paper investigates the challenging issue of designing an efficient soft-decision decoder for Cortex codes. A dedicated algorithm is introduced that takes advantage of the particular structure of the code to simplify the decoding. Simula...
Article
Full-text available
This paper deals with the presentation of different multiuser detectors in the Universal Mobile Telecommunications System (UMTS) context. The challenge is always to optimize the compromise between performance and complexity. Compared with the solution commonly used today, the rake detector, successive interference cancellation (SIC) detector has be...
Chapter
Introduction Concatenation of block codes Soft decoding of block codes Iterative decoding of product codes Conclusion Bibliography
Article
Full-text available
Ultra high-speed block turbo decoder architectures meet the demand for even higher data rates and open up new opportunities for the next generations of communication systems such as fiber optic transmissions. This paper presents the implementation, onto an FPGA device of an ultra high throughput block turbo code decoder. An innovative architecture...
Conference Paper
This article presents an innovative turbo product code (TPC) decoder architecture without any interleaving resource. This architecture includes a full-parallel SISO decoder able to process n symbols in one clock period. Syntheses show the better efficiency of such an architecture compared with existing previous solutions. Considering a 6-iteration...
Conference Paper
Full-text available
In this paper, the use of single-error-correcting Reed-Solomon (RS) product codes are investigated in an ultra high-speed context. A full-parallel architecture dedicated to the turbo decoding process of RS product codes is described. An experimental setup composed of a Dinigroup board that includes six Xilinx Virtex-5 LX330 FPGAs is employed. Thus,...
Conference Paper
In this paper, we demonstrate the higher hardware efficiency of Reed-Solomon (RS) parallel turbo decoding compared with BCH parallel turbo decoding. Based on an innovative architecture, this is the first implementation of fully parallel RS turbo decoder. A performance analysis is performed showing that RS block turbo codes (RS-BTC) have decoding pe...
Article
Full-text available
Turbo product codes (TPCs) are an attractive solution to improve link budgets and reduce systems costs by relaxing the requirements on expensive optical devices in high capacity optical transport systems. In this paper, we investigate the use of Reed-Solomon (RS) turbo product codes for 40Gbps transmission over optical transport networks and 10Gbps...
Conference Paper
Full-text available
This paper presents the implementation, on an FPGA device of an ultra high rate block turbo code decoder. First, a complexity analysis of the elementary decoder leads to a low complexity decoder architecture (area divided by 2) for a negligible performance degradation. The resulting turbo decoder is implemented on a Xilinx Virtex II-Pro FPGA in a c...
Conference Paper
Full-text available
We study the minimum distance of the binary expansion of high-rate Reed-Solomon (RS) codes and product codes in the polynomial basis and show that the binary codes obtained in this way usually have minimum distance equal to the designed symbol minimum distance. We then show that a judicious choice for the code roots may yield binary expansions with...
Article
Dans cet article, nous proposons une étude de complexité permettant d'optimiser l'architecture d'un décodeur élémentaire BCH en minimisant la dégradation des performances. Ce décodeur simplifié est inclus dans une architecture innovante de turbo décodeur de codes produits sans mémoire d'entrelacement. Un prototype a été réalisé sur un circuit FPGA,...
Article
This paper presents a new circuit architecture for turbo decoding, which achieves ultra high data rates when using product codes as error correcting codes. This architecture is able to decode product codes using binary BCH or m-ary Reed Solomon component codes. The major advantage of our full-parallel architecture is that it enables the memory bloc...
Article
Full-text available
This paper presents a new circuit architecture for turbo decoding, which achieves ultra high data rates when using product codes as error correcting codes. This architecture is able to decode product codes using binary BCH or m-ary Reed Solomon component codes. The major advantage of our full-parallel architecture is that it enables the memory bloc...
Article
Full-text available
A full-parallel architecture for turbo decoding, which achieves ultra high data rates when using product codes as error correcting codes, is proposed. This architecture is able to decode product codes using binary BCH or m-ary Reed Solomon component codes. The major advantage of our architecture is that it enables the memory blocks between all half...
Article
Full-text available
A row-column parallel architecture of a turbo decoder dedicated to product codes is presented. This architecture enables simultaneous decoding of the row and the column of a block. The performance of the proposed row-column parallel turbo decoder is similar to that of a conventional turbo decoder. However, this new architecture reduces the decoding...
Conference Paper
In this paper, the first flexible architecture dedicated to block turbo decoders is presented The major innovation concerns the component code that is used by the block turbo code. In fact, our architecture is able to decode BCH and Reed-Solomon codes with single or double correction power. To the authors' knowledge, this is the first architecture...
Article
The main purpose of this paper is to present a new turbo decoding architecture for high data rates with strong error correction power. We present the latest results on the block turbo decoder designs of product codes, using extended BCH codes correcting one and three errors. We present the architecture for decoding the product code BCH (32,26,4) ⊗...
Conference Paper
Reed-Solomon codes are block-based error correcting codes with a wide range of applications in digital communications and storage. Recently, block turbo codes using Reed-Solomon component codes have been introduced. This was motivated by the highest code rate property of Reed-Solomon codes and their efficiency for burst error correction. In fact, t...
Conference Paper
Full-text available
More than ten years after their introduction, turbo Codes are now a mature technology that has been rapidly adopted for application in many commercial transmissions systems. This paper provides an overview of the basic concepts employed in convolutional and block turbo codes, and review the major evolutions in the field with an emphasis on practica...
Article
Cet ouvrage débute par un exposé sur la théorie de l'information en mettant l'accent sur la mesure quantitative de l'information et en introduisant les deux théorèmes fondamentaux sur le codage de source et de canal. Il se poursuit en traitant des bases du codage de canal sous forme de deux chapitres, le premier étant consacré aux codes en blocs et...
Article
Full-text available
- Cet article propose une nouvelle architecture de turbo décodage de codes BCH (128,106,8) à entrées et sorties pondérées corrigeant 3 erreurs. En utilisant le concept de parallélisme et les propriétés de la matrice générée par un code produit, cet article présente la conception et la complexité de trois décodeurs capables de traiter 2, 4 et 8 donn...
Conference Paper
This paper presents a new circuit architecture for turbo decoding, which achieves very high data rates when using product codes as error correcting codes. Although this architecture is independent of the elementary code (convolutional or block) used and of the corresponding decoding algorithms, we focus here on the case of product codes. This innov...
Chapter
An iterative decoding algorithm (“Block Turbo Code (BTC) algorithm”) for product codes based on soft decoding and soft decision output of the component codes was introduced by R. Pyndiah in 1994 [1][2]. It uses the concepts developed by C. Berrou who proposed a technique to encode and decode a class of error correcting codes, called “Turbo codes” C...
Article
This paper presents a block turbo decoding algorithm, from its theory to its implementation in a programmable circuit. In this study, we discuss the two prototypes realized. It will be possible to compare the complexity of the core of the process, which is the elementary decoder, thanks to the choice of essential parameters. One prototype is more d...
Conference Paper
This paper presents two implementations of the same block turbo decoding algorithm: on the one hand an elementary decoder in association with a sequencer performs the complete turbo decoding process, and on the other hand, the circuit contains one elementary decoder per half-iteration. The choice of different parameters for each algorithm implement...
Article
Full-text available
Ce papier propose une nouvelle architecture d'un turbo décodeur, permettant de traiter un débit d'information élevé et utilisant comme code correcteur d'erreurs un code produit. Elle est indépendante du code élémentaire choisi (convolutif ou en bloc linéaire) et de l'algorithme de décodage utilisé. Elle prend en compte le parallélisme lié aux propr...
Article
This paper presents the latest results on a block turbo decoder design. We propose a block turbo decoder circuit for the error protection of small data blocks such asAtm cells on anAwgn (additive white Gaussian noise) channel with a code rate close to 0.5. A prototype was developed atEnst Bretagne. It allowsBer (bit error rate) measurements down to...
Article
- Cet article présente la conception d'un décodeur BCH (32,19,6) à entrées et sorties pondérées corrigeant 2 erreurs. La cible technologique choisie, circuit intégré programmable (FPGA XILINX), ainsi que sa faible complexité (20000 portes), a permis son insertion dans une maquette de turbo décodage qui autorise des mesures de taux d'erreurs de l'or...
Article
Full-text available
Cet article propose une étude comparée entre algorithme et architecture en vue de l'implantation sur silicium et plus particulièrement sur FPGA d'un circuit de turbo-décodage de codes BCH(128,120,4). L'utilisation du langage C - pour les simulations - et du VHDL - pour la synthèse - permettent de comparer les performances et la complexité du circui...
Chapter
This paper presents a practical course followed by 2nd year students at the Ecole Nationale Supérieure des Télécommunications de Bretagne. During this practical course students have the opportunity to design an integrated circuit using the Ping-Pong technique. Field Programmable Gate Array technology is used in order to allow the circuit to be test...
Article
The authors present the latest results on turbo codes which are built from a serial concatenation between a block code (BCH) and a recursive systematic convolutional code. The performance on a Gaussian channel with QPSK modulation is evaluated
Conference Paper
This paper presents a low complexity block turbo decoder for product codes. This new decoder, which has been derived from the near-optimum block turbo decoder is a very good compromise between complexity and performance. For performance evaluation, we have considered the [BCH(64,57,4)]<sup>2</sup> product code transmitted over a Gaussian channel us...
Conference Paper
This paper presents the latest results on block turbo codes and also an analysis of the possible implementations of a block turbo decoder circuit. Simulation results show that the SNR (signal to noise ratio) required to achieve a BER (Bit Error Rate) of 10<sup>-5</sup> with block turbo codes is 2.5±0.2 dB from their Shannon limit for any code rate....
Conference Paper
Recently, a new family of error correcting codes called turbo-codes, has been developed. An original auto-synchronisation method for these turbocodes is reported. This method ensures the timing synchronisation necessary to trigger the internal functions of turbo-decoders like interleaving or deinterleaving. This technique also takes into account el...
Article
Cet article aborde l'intégration sur silicium d'un algorithme original de décodage itératif des codes produits à entrée et sorties pondérées. Les performances de cet algorithme en terme de taux d'erreurs binaires sont aussi bonnes que celles des turbo-codes convolutifs. Les solutions proposées, tant pour l'architecture du circuit que pour la mémori...
Conference Paper
A means to adapt the classical architecture of a Viterbi decoder to make it able to provide soft (weighted) decisions is presented. After a theoretical justification of the proposed method, based on Battail or Hagenauer-Hoeher algorithms, the new architecture is detailed. It leads to a real-time circuit, the size of which is roughly twice the size...
Conference Paper
Describes the framework and the design method used for an integrated circuit achieving ping-pong control for digital synchronous links. The principles of time division duplex communications and the different choices required for circuit design are also explained
Article
High code rate BTC (Block Turbo Codes) have already demonstrated excellent performance for me- dium size modulations (QPSK, 16-QAM) on AWGN or Rayleigh fading channels. This paper considers new applica- tions for these codes. First we consider very large QAM constellations for the DSL application. For a 256-QAM modulation, 10 -6 BER (Bit Error Rate...
Article
Full-text available
Research activities of the electronic engineering department are concerned with Algorithm-Architecture-Matching approach for iterative processing ("turbo" principle) in the digital communications systems. The turbo principle is a general way of processing data in receivers so that no information is wasted. Our work is about all aspects of mapping a...
Article
Après avoir défini les principes des communications par duplexage temporel, cet article présente le fonctionnement d'un circuit intégré contrôleur d'alternat pour liaisons numériques synchrones. Les différents choix nécessaires à sa réalisation y sont explicités.
Article
Cet article présente l'architecture d'un décodeur de Viterbi utilisant la méthode du "Register Exchange Algorithm" et capable de fournir des décisions pondérées à sa sortie. L'algorithme de pondération mis en oeuvre dans cette architecture, est basé sur celui de Battait ou de Hagenauer-Hoeher et peut être réalisé sur un circuit intégré monolithique...
Article
Full-text available
Cet article présente les derniers résultats concernant les turbo codes en blocs, obtenus à partir de codes BCH étendus. Après avoir rappelé l'algorithme itératif de décodage utilisé, nous évaluons la complexité des turbo décodeurs associés. Nous proposons des simplifications dans le calcul de la pondération et dans la mise en oeuvre de l'algorithme...
Article
Full-text available
Cet article présente les étapes préparatoires à l'implantation d'un récepteur multi-utilisateurs appliqué à la liaison montante du système UMTS. Tout d'abord, la comparaison des résultats des simulations d'une détection mono-utilisateur à base de Filtre Adapté avec une détection multi-utilisateurs à suppression d'interférence successive (SIC) dans...

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