Nuria Pazos

Nuria Pazos
Arc Engineering High School · Embedded Computing Systems Group

About

27
Publications
4,216
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240
Citations

Publications

Publications (27)
Article
Full-text available
Standard-sized autonomous vehicles have rapidly improved thanks to the breakthroughs of deep learning. However, scaling autonomous driving to mini-vehicles poses several challenges due to their limited on-board storage and computing capabilities. Moreover, autonomous systems lack robustness when deployed in dynamic environments where the underlying...
Article
The spread of deep learning on embedded devices has prompted the development of numerous methods to optimise the deployment of deep neural networks (DNN). Works have mainly focused on: i) efficient DNN architectures, ii) network optimisation techniques such as pruning and quantisation, iii) optimised algorithms to speed up the execution of the most...
Article
Next generation of embedded Information and Communication Technology (ICT) systems are interconnected and collaborative systems able to perform autonomous tasks. The remarkable expansion of the embedded ICT market, together with the rise and breakthroughs of Artificial Intelligence (AI), have put the focus on the Edge as it stands as one of the key...
Preprint
Autonomous navigation vehicles have rapidly improved thanks to the breakthroughs of Deep Learning. However, scaling autonomous driving to low-power and real-time systems deployed on dynamic environments poses several challenges that prevent their adoption. In this work, we show an end-to-end integration of data, algorithms, and deployment tools tha...
Preprint
The spread of deep learning on embedded devices has prompted the development of numerous methods to optimise the deployment of deep neural networks (DNN). Works have mainly focused on: i) efficient DNN architectures, ii) network optimisation techniques such as pruning and quantisation, iii) optimised algorithms to speed up the execution of the most...
Preprint
Deep Learning is increasingly being adopted by industry for computer vision applications running on embedded devices. While Convolutional Neural Networks' accuracy has achieved a mature and remarkable state, inference latency and throughput are a major concern especially when targeting low-cost and low-power embedded platforms. CNNs' inference late...
Conference Paper
Deep Learning is moving to edge devices, ushering in a new age of distributed Artificial Intelligence (AI). The high demand of computational resources required by deep neural networks may be alleviated by approximate computing techniques, and most notably reduced-precision arithmetic with coarsely quantized numerical representations. In this contex...
Conference Paper
Full-text available
The Bonseyes EU H2020 collaborative project aims to develop a platform consisting of a Data Marketplace, a Deep Learning Toolbox, and Developer Reference Platforms for organizations wanting to adopt Artificial Intelligence. The project will be focused on using artificial intelligence in low power Internet of Things (IoT) devices ("edge computing"),...
Conference Paper
This paper presents a real-world proven solution for dynamic street light control and management which relies on an open and flexible Internet of Things architecture. Substantial contribution is brought at the interoperability level using novel device connection concept based on model-driven communication agents to speed up the integration of senso...
Conference Paper
Full-text available
This paper presents a novel approach towards dynamic street light control, which combines advanced Information and Communication Technologies (ICT) and citizens’ involvement and engagement. Our proposal is based on the Citizens’ involvement which would strongly increases the efficiency and performance of technological solutions in smart city contex...
Conference Paper
Recently advances in the design of general purpose SoC have revolutionized the conception of embedded systems, thanks to the availability of several, most of the time asymmetric, units of calculation. Nevertheless a deep knowledge of the internal hardware architecture of these multi-core SoC is required to efficiently benefit from its large computi...
Conference Paper
This work envisions a feasible solution for faster convergence towards a flexible and robust design alternative for the global wires encountered in a SoC. The application of the proposed approach based on early wire characterization to the global interconnects of a Network-on-Chip (NoC), clearly shows that the novel method can converge the design t...
Chapter
The design of emerging networking architectures opens a multiple scenario of alternatives. If the design starts at a higher level of abstraction the process towards the selection of the optimal target architecture, as well as the partitioning of the functionalities, can be considerably accelerated. The present work introduces a novel system level p...
Article
Full-text available
This work envisions a common design methodology, applicable for every interconnect level and based on early wire characterization, to provide a faster convergence to a feasible and robust design. We claim that such a novel design methodology is vital for upcoming nanometer technologies, where increased variations in both device characteristics and...
Conference Paper
Full-text available
Networks-on-chip (NoC) are emerging as a widely accepted alternative for the traditional bus architectures. However, their applicability by the system designers is far away from being intuitive due to their lack of predictability. This communication predictability can be obtained statically or dynamically. A dynamic allocation is more suitable for...
Article
Networks-on-Chip are emerging as a widely accepted alternative for the traditional bus architectures. However, their applicability by the system designers is far away from being intuitive due to their lack of predictability. This communication predictability can be obtained statically or dynamically. A dynamic allocation is more suitable for flexib...
Conference Paper
Constructive algorithms for mapping and scheduling take advantage of short execution times. However, since decisions for the mapping have to be made at a time when not all information of dynamic effects is available, unfavorable situations can arise which result in a degraded performance. In this paper, an enhancement for a constructive algorithm i...
Article
Full-text available
This paper describes two different approaches to optimize the performance of SoC architectures in the architecture exploration phase. Both solve the problem to map and schedule a task graph on a target architecture under special consideration of on-chip communications. A constructive algorithm is presented that extends previous work by taking into...
Conference Paper
Networking devices have to offer short processing latencies and flexibility concerning the supported networking protocols and applications. The input packet-processing flow in conventional networking node devices follows a serial or a layer-specific pseudo-parallel method, serialized by the data dependencies of the inherent layer protocol types. Th...
Conference Paper
This article describes a packet processing methodology, which executes the required protocol layer functions of a networking device in parallel. Based on the dynamic prediction of the inherent protocol-stack of receiving packets, the data dependency of the layers is speculatively resolved and the functions are processed. Consequently, packet proces...
Article
In der Arbeit wird eine neue, auf der Sprache SystemC basierende Methode zur Abschätzung der Performance bei der Exploration von Architekturalternativen auf System-Ebene entwickelt. Wesentlich bei diesem Ansatz ist, dass kein aufwendiger Umbau des Modells erforderlich ist, um verschiedene Hardware-Software Partitionierungsalternativen auch bei Ände...

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