Neha Arora

Dhirubhai Ambani Institute of Information and Communication Technology | DA-IICT · Research Group for VLSI Design

ECG is a non-invasive way of determining cardiac health by measuring the electrical activity of the heart. We investigate a novel detection technique for feature points P, QRS and T to diagnose various atrial and ventricular cardiovascular anomalies with ECG signals for ambulatory monitoring. Before the system is worthy of field trials, we validate...

Over the years researchers have studied the evolution of Electrocardiogram (ECG) and the complex classification of cardiovascular diseases. This review focuses on the evolution of the ECG, and covers the most recent signal processing schemes with milestones over last 150 years in a systematic manner. Development phases of ECG, ECG leads, portable E...

Over the years, researchers have studied the evolution of Electrocardiogram (ECG) and the complex classification of cardiovascular diseases. This review focuses on the evolution of the ECG and covers the most recent signal processing schemes with milestones over the last 150 years systematically. Development phases of ECG, ECG leads, portable ECG m...

The Array architecture is a popular technique to implement the multipliers due to its compact structure. In this paper, 2x2 array multiplier circuits using existing full adder and DCVS logic full adder have been designed, simulated, analyzed and compared. An extensive analysis of multipliers has been done. According to our test results, an array mu...

In modern era, the demand for memory has been increases tremendously. Due to reduction in SRAM operating voltage, cell stability degradation and the increase in process variation with process scaling. This paper presents a proposed 10T SRAM cell based on a gated-ground nMOS transistor technique and reduces the total leakage power consumption of SRA...

In recent years the demand for low power devices has been increases tremendously. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between power, delay and area, thus designers are required to choos...

A multiplexer, sometimes referred to as a "mux", is a device that selects between a numbers of input signals. It is a combinational logic circuit. It is a unidirectional device and used in any application in which data must be switched from multiple sources to a destination. This paper represents the simulation of different 2:1 Multiplexer Structur...

This paper enumerates low power, high speed design of D flip-flop. It presents various techniques to minimize subthreshold leakage power as well as the power consumption of the CMOS circuits. The proposed circuit in this paper shows a design for D flip flop to increase the overall speed of the system as compared to other circuits. This technique al...

This paper presents new design techniques for adiabatic full adder cell. Adiabatic logic is the most efficient energy saving technique which provides very low power dissipation in VLSI circuits. Adiabatic Full adder is simulated by using different adiabatic techniques. Simulation results show that energy loss of adiabatic circuits can be greatly re...

A novel low-power and high-speed master-salve Latches is proposed in this paper, thus the improvement of flip-flops and latches is one of the most critical tasks to enhance the system performance. The circuits are simulated on Tanner EDA tool with BSIM3V3 45nm CMOS technology for the calculation and comparison power delay product and both PDP and d...

The architectural technique described in this paper suggests a design to minimize area and capacitance by using Gate Diffusion Input (GDI) multiplexer. By utilizing the leakage current of devices working in subthreshold region, we propose a method to reduce the leakage power of D flip flops in this paper by using GDI technique. Implementing and sim...

Adiabatic circuits and standard CMOS logic are widely employed in Low power VLSI chips to achieve high system performance. The power saving of adiabatic circuit can reach more than 90% compared to conventional static CMOS logic.The clocking schemes and signal waveforms of adiabatic are different from those of standard CMOS circuits. This paper inve...

In VLSI, as the complexity of the chip is increasing, length of interconnect and number of repeaters are also increasing. The power delay product and frequency of operation plays significant role in designing of repeater. Simulations and calculations for various lengths of interconnect with the earlier conventional repeater and proposed repeater ar...

Adiabatic circuits and standard CMOS logic are widely employed in Low power VLSI chips to achieve high system performance. The power saving of adiabatic circuit can reach more than 90% compared to conventional static CMOS logic.The clocking schemes and signal waveforms of adiabatic circuits are different from those of standard CMOS circuits. This p...

In today's IC design, one of the key challenges is the increase in power dissipation of the circuit and packaging costs of these circuits shortens the service time of battery and also reduces the long term reliability. The demand for static random-access memory (SRAM) is increasing with large use of SRAM in System On-Chip and high-performance VLSI...