Naser Mohammadzadeh

Naser Mohammadzadeh
Shahed University · Department of Computer Engineering

Doctor of Engineering

About

32
Publications
3,512
Reads
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212
Citations
Additional affiliations
May 2016 - December 2018
Shahed University
Position
  • Professor (Associate)
January 2007 - December 2010
Amirkabir University of Technology
Position
  • Research Assistant
September 2003 - September 2007
Sharif University of Technology
Position
  • Research Assistant
Education
January 2007 - December 2010
Amirkabir University of Technology
Field of study
  • Ph.D. Computer System Architeture
September 2003 - September 2005
Sharif University of Technology
Field of study
  • M.Sc. Computer System Architecture
September 1999 - September 2003
Sharif University of Technology
Field of study
  • B.Sc. Computer System Architecture

Publications

Publications (32)
Article
Full-text available
The physical synthesis concept for quantum circuits, the interaction between synthesis and physical design processes, was first introduced in our previous work. This concept inspires us to propose some techniques that can minimize the number of extra inserted SWAP operations required to run a circuit on a nearest-neighbor architecture. Minimizing t...
Article
Full-text available
Developing a scalable quantum computer as a single processing unit is challenging due to technology limitations. A solution to deal with this challenge is distributed quantum computing where several distant quantum processing units are used to perform the computation. The main design issue of this approach is costly communication between the proces...
Article
In recent years, many studies have been focused on designing quantum circuits for the promising future of quantum computers. In these studies, latency has been considered as one of the main performance measures in quantum circuit design. This paper proposes a congestion‐aware mixed integer linear programming model for placement and scheduling of qu...
Article
Proposing an architecture that efficiently compensates for the inefficiencies of physical hardware with extra resources is one of the key issues in quantum computer design. Although the demonstration of quantum systems has been limited to some dozen qubits, scaling the current small-sized lab quantum systems to large-scale quantum systems that are...
Article
Full-text available
Distinct practical advantages of the one-way quantum computation (1WQC) have attracted the attention of many researchers. To physically realize a 1WQC pattern, its qubits should be mapped onto a quantum physical environment. The nearest-neighbor architectures are suitable for implementing 1WQC patterns because they provide nearest-neighbor sufficie...
Article
Full-text available
Similar to traditional CMOS circuits, quantum circuit design flow is divided into two main processes: logic synthesis and physical design. Addressing the limitations imposed on optimization of the quantum circuit metrics because of no information sharing between logic synthesis and physical design processes, the concept of “physical synthesis” was...
Conference Paper
Recent development in information technology and internet makes the internet of things (IoT) more popular than before. Since all of entities can be interact with each other, so some security elements such as authentication should be considered. Sensor-to-Sensor connection is one of the important communications in IoT environment. Therefore in this...
Conference Paper
This paper presents a partial-parallel LDPC decoder based on sum-product algorithm with high throughput. The hardware implementation of decoder considers design issues with respect to FPGA and time scheduling is proposed based on modified TPMP 1 algorithm in order to reduce the number of clock cycles, hardware resources and power. The decoder is im...
Article
Quantum circuits have indicated incredible potential for having the capacity to take care of specific issues, which are unmanageable on classical machines. Research in quantum circuit design distinguishes between logic synthesis and physical design. In this survey, we review the approaches, exact and heuristic, proposed for physical design automati...
Article
Full-text available
One of the main features of nodes in mobile ad hoc networks (MANETs) is their cooperation with neighbors to propagate data. Misusing this feature, malicious nodes cooperate with normal nodes to disrupt network operation and reduce its efficiency. These nodes attack other network nodes and prevent being detected by other nodes through using the mobi...
Article
Physical design is the second process in the design flow of quantum circuits that receives a netlist as input and generates a layout at a target technology. Quantum physical design problem is intractable. This process tackles the operation scheduling, placement, and qubit routing problems. Some approaches have been proposed for the physical design...
Article
Recent works on quantum physical design have pushed the scheduling and placement of quantum circuit into their prominent positions. In this article, a mixed integer nonlinear programming model is proposed for the placement and scheduling of quantum circuits in such a way that latency is minimized. The proposed model determines locations of gates an...
Article
Full-text available
Physical design and synthesis are two key processes of quantum circuit design methodology. The physical design process itself decomposes into scheduling, mapping, routing, and placement. In this paper, a mathematical model is proposed for mapping, routing, and scheduling in ion-trap technology in order to minimize latency of the circuit. The propos...
Article
Full-text available
In our previous works, we have introduced the concept of "physical synthesis" as a method to consider the mutual effects of quantum circuit synthesis and physical design. While physical synthesis can involve various techniques to improve the characteristics of the resulting quantum circuit, we have proposed two techniques (namely gate exchanging an...
Conference Paper
Full-text available
Quantum circuit design flow consists of two main tasks: synthesis and physical design. Synthesis converts the design description into a technology-dependent netlist and then, physical design takes the fixed netlist, produces the layout, and schedules the netlist on the layout. Quantum physical design problem is intractable. This process can be divi...
Article
During the physical design process, the second process of the quantum circuit design flow, using some optimization techniques after layout generation might be useful to improve the metrics or meet the design constraints. Focusing on this issue, this paper proposes an optimization technique using gate location changing to improve the latency of quan...
Article
Full-text available
Quantum circuit design flow consists of two main tasks: synthesis and physical design. Addressing the limitations imposed on optimization of the quantum circuit objectives because of no information sharing between synthesis and physical design processes, we introduced the concept of “physical synthesis” for quantum circuit flow and proposed a techn...
Article
Quantum circuit design flow consists of two main tasks: synthesis and physical design. In the current flows, two procedures are performed subsequently and without any information sharing between two processes that can limit the optimization of the quantum circuit metrics; synthesis converts the design description into a technology-dependent netlist...
Conference Paper
Quantum circuit design flow consists of two main tasks: synthesis and physical design. In the current flows, two procedures are performed subsequently; synthesis converts the design description into a technology-dependent netlist and then physical design takes the fixed netlist, produces layout, and schedules the netlist on the layout. This style o...
Conference Paper
Full-text available
Multi-domain clock skew scheduling is a cost effective technique for performance improvement. However, the required wire length and area overhead due to phase shifters for realizing such clock scheduler may be considerable if registers are placed without considering assigned skews. Focusing on this issue, in this paper, we propose a skew scheduling...
Article
The growing complexity of today's embedded systems demands new methodologies and tools to manage the problems of analysis, design, implementation, and validation of complex-embedded systems. Focusing on this issue, this paper describes a design and implementation toolset using our ODYSSEY methodology, which advocates object-oriented (OO) modeling o...
Article
Design technology is expected to rise to electronic system-level (ESL). This necessitates new techniques and tools for synthesizing ESL designs and for verifying them before and after ESL synthesis. A promising verification strategy for future very complex designs is to initially verify the design at the highest level of abstraction, and then check...
Conference Paper
Full-text available
Existing synthesis-related cost functions are explored and five fundamental properties of an efficient quantum circuit implementation are introduced. In addition, a thorough set of metrics for quantum circuit synthesis are proposed and applied on some well-known synthesis algorithms. Our analysis reveals the requirement of proposing new synthesis a...
Article
The Network-on-Chip (NoC) paradigm brings networks inside chips. We use the routing capabilities inside NoC to serve as a replacement for Virtual Method Table (VMT) for Object-Oriented (OO) designed hardware/software co-design systems where some methods could be implemented as hardware modules. This eliminates VMT area and performance overhead in O...
Conference Paper
Full-text available
In this paper, we present a JPEG decoder implemented in our ODYSSEY design methodology. We start with an object-oriented JPEG decoder model. The total operation from modeling to implementation is done automatically by our EDA tool-set in about 10 hours. The resultant system is a JPEG decoder ASIP whose hardware part is implemented on FPGA logic blo...
Conference Paper
Full-text available
In this paper, we present an MPEG-2 video decoder implemented in our ODYSSEY design methodology. We start with an ASIP tailored to the JPEG decompression algorithm. We extend that ASIP by required software routines such that the extended ASIP can now perform MPEG2 decoding while still benefiting from hardware units common between JPEG and MPEG2. Th...
Article
Full-text available
A fault-tolerant approach for application-specific instruction-set processor (ASIP) to reduce the cost of classical fault-tolerant mechanisms is presented in this paper. The ASIP is synthesized from an object-oriented high-level description by a hardware- software co-design approach and consists of a processor core along with some functional units....

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