Nandeesh Veeranna

Nandeesh Veeranna
The Hong Kong Polytechnic University | PolyU · Department of Electronic and Information Engineering

Doctor of Philosophy

About

10
Publications
3,340
Reads
How we measure 'reads'
A 'read' is counted each time someone views a publication summary (such as the title, abstract, and list of authors), clicks on a figure, or views or downloads the full-text. Learn more
71
Citations
Citations since 2017
7 Research Items
69 Citations
2017201820192020202120222023051015
2017201820192020202120222023051015
2017201820192020202120222023051015
2017201820192020202120222023051015
Additional affiliations
September 2015 - December 2015
The Hong Kong Polytechnic University
Position
  • Research Assistant
Description
  • Teaching assistant for the course EIE511 for Master students.
January 2015 - May 2015
The Hong Kong Polytechnic University
Position
  • Research Assistant
Description
  • Teaching assistant for the course VLSI cad EIE4110 for undergraduates.
July 2014 - July 2017
The Hong Kong Polytechnic University
Position
  • PhD
Education
September 2011 - August 2013
Rashtreeya Vidyalaya College of Engineering
Field of study
  • VLSI design and Embedded Systems
September 2006 - July 2010
Siddaganga Institute of Technology
Field of study
  • Electronics and communication Engineering

Publications

Publications (10)
Chapter
Obfuscation is an easy and inexpensive way to protect intellectual property (IP). When obfuscating an IP, a functional equivalent source file is generated, which is virtually impossible for humans to understand and extremely difficult to reverse engineer. Source code obfuscation typically removes comments, renames variables, and adds redundant expr...
Preprint
Full-text available
Timing side-channel attacks pose a major threat to embedded systems due to their ease of accessibility. We propose CIDPro, a framework that relies on dynamic program diversification to mitigate timing side-channel leakage. The proposed framework integrates the widely used LLVM compiler infrastructure and the increasingly popular RISC-V FPGA soft-pr...
Conference Paper
Full-text available
Timing side-channel attacks pose a major threat to embedded systems due to their ease of accessibility. We propose CIDPro, a framework that relies on dynamic program diversification to mitigate timing side-channel leakage. The proposed framework integrates the widely used LLVM compiler infrastructure and the increasingly popular RISC-V FPGA soft-pr...
Presentation
Full-text available
Slides of the oral presentation of the corresponding paper (https://www.researchgate.net/publication/327495855_CIDPro_Custom_Instructions_for_Dynamic_Program_Diversification)
Article
Full-text available
This work presents an open-source benchmark suite of synthesizable behavioral descriptions with different types of hardware Trojan. A repository of RT-level benchmarks with different types of Hardware Trojan is available at the Trust-hub (https://www.trust-hub.org/resources/benchmarks). Unfortunately, this benchmark suite misses completely the beha...
Article
Full-text available
This work introduces a runtime system level method to detect hardware Trojan in third party behavioral intellectual properties (3PBIPs). Most of the HW Trojan detection techniques either rely on golden Trojan-free (trusted) models, which are compared to the suspected model, or source IPs with the same functionality from different vendors. In the ca...
Conference Paper
Obfuscation is an easy and inexpensive way to protect Intellectual Property (IP). When obfuscating an IP, a functional equivalent source file is generated, which is virtually impossible for humans to understand and extremely difficult to reverse-engineer. The obfuscation process typically removes comments, renames variables and adds redundant expre...
Conference Paper
Most prior work on hardware reliability make use of module (spatial) redundancy or time redundancy. In the first case, these methods assume that each module is exactly the same. Multiple module replicas implementing the same logic function are executed in different hardware channels and a voting scheme detects if the outputs match or not. In the se...
Article
This work introduces a fully automatic method to detect the presence of HW Trojans in third party behavioral IPs (3PBIPs) using formal verification methods. In particular, property checking at the behavioral level. Some state of the art HLS tools now also include advanced formal verification tools. This work leverages these tools to detect the mali...

Questions

Question (1)
Question
Suppose I have an initial population (Chromosomes) P={P1, P2, P3, P4, ......., Pn}. If I do crossover on two random parents (P1XP2) by choosing random symmetrical points in P1 and P2. I name the generated off springs as Poff_1 and Poff_2.
My question is, whether the mutation is performed on the chromosomes (off springs) generated after cross over, i.e., on Poff_1 and Poff_2 or on the chromosomes from initial population P?
Also, how to choose the parents based on the crossover probability Pc? Suppose if I fix the cross over probability to be 0.78 (ranges from 0.5 to 1.0 according to survey), how to choose the 78% parents from the set P.

Network

Cited By