# Morteza Saheb ZamaniAmirkabir University of Technology | TUS · Department of Computer Engineering and Information Technology

Morteza Saheb Zamani

Professor

## About

126

Publications

12,999

Reads

**How we measure 'reads'**

A 'read' is counted each time someone views a publication summary (such as the title, abstract, and list of authors), clicks on a figure, or views or downloads the full-text. Learn more

948

Citations

Introduction

Additional affiliations

August 2016 - January 2017

January 2003 - December 2012

January 1996 - June 1996

## Publications

Publications (126)

The trustability of integrated circuits (ICs) has become a serious issue due to the outsourcing of IC manufacturing to third-party foundries. Given reports of IC tampering, extensive research activities have focused on finding appropriate solutions to prevent this issue. This paper proposes an approach to detect hardware Trojans using a design meth...

FPGAs are increasingly becoming sensitive to aging effects mainly through BTI phenomena in the latest technology nodes. This phenomenon can be modeled as a shift in the threshold voltage of transistors which leads to performance degradation and reduction in SNM of SRAM cells. To reduce the aging effects on FPGA building blocks, we propose FIFA, a f...

With the rapid increase in digital technologies, most fields of study include recognition of human activity and intention recognition, which are important in smart environments. In this research, we introduce a real-time activity recognition to recognize people's intentions to pass or not pass a door. This system, if applied in elevators and automa...

Developing a scalable quantum computer as a single processing unit is challenging due to technology limitations. A solution to deal with this challenge is distributed quantum computing where several distant quantum processing units are used to perform the computation. The main design issue of this approach is costly communication between the proces...

FPGA devices are highly susceptible to transistor aging, mainly through Bias Temperature Instability (BTI) phenomenon. BTI can be modeled as threshold voltage increase in MOSFET transistors which leads to device performance degradation. As technology scales, leakage power has turned into a major portion of FPGA total power consumption. In this pape...

Differential Power Analysis (DPA) attacks are known as viable and practical techniques to break the security of cryptographic algorithms. In this type of attack, an adversary extracts the encryption key based on the correlation of consumed power of the hardware running encryption algorithms to the processed data. To address DPA attacks in the hardw...

In one-way quantum computation (1WQC) model, an initial highly entangled state called a graph state is used to perform universal quantum computations by a sequence of adaptive single-qubit measurements and post-measurement Pauli-X and Pauli-Z corrections. The needed computations are organized as measurement patterns, or simply patterns, in the 1WQC...

In this paper, a system architecture is proposed that closely models the functionality of metabolic networks. The AND/OR graph model is used to represent the metabolic network and each processing element in the system emulates the functionality of a metabolite. The system is implemented on a graphical processing unit (GPU) as the hardware platform...

As there is no quantum error correction code with universal set of transversal gates, several approaches have been proposed which, in combination of transversal gates, make universal fault-tolerant quantum computation possible. Magic state distillation, code switching, code concatenation and pieceable fault-tolerance are well-known examples of such...

One-way quantum computation (1WQC) is a model of universal quantum computations in which a specific highly entangled state called a cluster state allows for quantum computation by single-qubit measurements. The needed computations in this model are organized as measurement patterns. The traditional approach to obtain a measurement pattern is by tra...

An Elementary Flux Mode (EFM) is a pathway with minimum set of reactions that are functional in steady-state constrained space. Due to the high computational complexity of calculating EFMs, different approaches have been proposed to find these flux-balanced pathways. In this paper, an approach to find a subset of EFMs is proposed based on a graph d...

In this paper we present a novel method for real time hardware implementation of Central Pattern Generators (CPGs) for bipedal robot walking. We introduce a closed form solution for Matsuoka CPG model which is a widely applied parametric neuron-based method for walking pattern generation. Existing parameter tuning methods including trial and error,...

Quantum-logic synthesis refers to generating a quantum circuit for a given arbitrary quantum gate according to a specific universal gate library implementable in quantum technologies. Previously, an approach called block-based quantum decomposition (BQD) has been proposed to synthesize quantum circuits by using a combination of two well-known quant...

As there is no quantum error correction code with universal set of transversal gates, several approaches have been proposed which in combination of transversal gates make universal fault-tolerant quantum computation possible. Magic state distillation, code switching, code concatenation etc. are well-known examples of such approaches. However, the o...

Using transversal gates is a straightforward and efficient technique for fault-tolerant quantum computing. Since transversal gates alone cannot be computationally universal, they must be combined with other approaches such as magic state distillation, code switching or code concatenation in order to achieve universality. In this paper we propose an...

Hardware Trojan detection has been the subject of many studies in the realm of hardware security in the recent years. The effectiveness of current techniques proposed for Trojan detection is limited by some factors, process variation noise being a major one. This paper introduces latch-based structures as a self-reference detection technique which...

In this article, the problem of synthesizing a general Hermitian quantum gate into a set of primary quantum gates is addressed. To this end, an extended version of the Jacobi approach for calculating the eigenvalues of Hermitian matrices in linear algebra is considered as the basis of the proposed synthesis method. The quantum circuit synthesis met...

Motivation:
A fundamental computational problem in the area of metabolic engineering is finding metabolic pathways between a pair of source and target metabolites efficiently. We present an approach, namely FogLight, for searching metabolic networks utilizing Boolean (AND-OR) operations represented in matrix notation to efficiently reduce the sear...

During the last few years, hardware Trojan horses (HTHs) have become one of the most important threats to the security of very large scale integrated (VLSI) chips. Many efforts have been made to facilitate the process of HTH detection, mostly based on the power analysis of chips. The techniques would be more beneficial if trust-driven techniques ar...

In one-way quantum computation (1WQC) model, universal quantum computations are performed using measurements to designated qubits in a highly entangled state. The choices of bases for these measurements as well as the structure of the entanglements specify a quantum algorithm. As scalable and reliable quantum computers have not been implemented yet...

Hardware Trojan horses (HTHs) are challenging threats to the security of silicon chips. A promising solution is path-delay fingerprinting for HTH detection. This paper presents trust-driven retiming , a synthesis approach to provide a circuit which can be analyzed more effectively by delay fingerprinting. To this end, TDR tries to reduce the maximu...

One-way quantum computation (1WQC) is a model of universal quantum computations in which a specific highly entangled state called a cluster state (or graph state) allows for quantum computation by only single-qubit measurements. The needed computations in this model are organized as measurement patterns. Previously, an automatic approach to extract...

Quantum logic decomposition refers to decomposing a given quantum gate to a
set of physically implementable gates. An approach has been presented to
decompose arbitrary diagonal quantum gates to a set of multiplexed-rotation
gates around z axis. In this paper, a special class of diagonal quantum gates,
namely diagonal Hermitian quantum gates, is co...

Stabilizer formalism is a powerful framework for understanding a wide class of operations in quantum information. This formalism is a framework where multiple qubit states and sub-spaces are described in a compact way in terms of operators under which they are invariant. In stabilizer formalism, one focuses the members of Pauli groups which have th...

In our previous works, we have introduced the concept of "physical synthesis" as a method to consider the mutual effects of quantum circuit synthesis and physical design. While physical synthesis can involve various techniques to improve the characteristics of the resulting quantum circuit, we have proposed two techniques (namely gate exchanging an...

Quantum circuit design flow consists of two main tasks: synthesis and physical design. Synthesis converts the design description into a technology-dependent netlist and then, physical design takes the fixed netlist, produces the layout, and schedules the netlist on the layout. Quantum physical design problem is intractable. This process can be divi...

Hardware Trojan horses (HTHs) are important threats to the trustworthiness of hardware chips. Design-forhardware-trust (DFHT) techniques are used to enhance the detectability of possible HTHs. Existing DFHT approaches are usually ad-hoc techniques. This characteristic makes them vulnerable to neutralization efforts. We study this concept by focusin...

Fault tolerance is a necessity for successful realization of quantum circuits. Achieving fault tolerance in quantum circuits is more complicated than classic circuits due to their inherent characteristics such as error continuum, destruction of quantum state after measurement, and no-cloning. Adding fault tolerance should incur a reasonably minimal...

Implementing large-scale quantum circuits is one of the challenges of quantum
computing. One of the central challenges of accurately modeling the
architecture of these circuits is to schedule a quantum application and
generate the layout while taking into account the cost of communications and
classical resources as well as the maximum exploitable...

The size of configuration bitstreams of field-programmable gate arrays (FPGA) is increasing rapidly. Compression techniques are used to decrease the size of bitstreams. In this paper, an appropriate bitstream format and variable symbol lengths are proposed to utilize the routing patterns for enhancing the compression efficiency. An order of inputs...

Comparing three-dimensional structure of proteins is one of the most fundamental problems in bioinformatics. In recent years, various algorithms have been proposed to solve this problem efficiently. The proposed algorithms are very time-consuming due to high complexity and large input data. In this paper, hardware acceleration is applied to minimiz...

In one-way quantum computation (1WQC) model, universal quantum computations are performed using measurements to designated qubits in a highly entangled state. The choices of basis for these measurements as well as the structure of the entanglements specify a quantum algorithm. Although a number of methods have been proposed to simulate quantum circ...

In this paper, simultaneous reduction of circuit depth and synthesis cost of
reversible circuits in quantum technologies with limited interaction is
addressed. We developed a cycle-based synthesis algorithm which uses negative
controls and limited distance between gate lines. To improve circuit depth, a
new parallel structure is introduced in which...

In one-way quantum computations (1WQC), quantum correlations in an entangled state, called a cluster or graph state, are exploited to perform universal quantum computations using single-qubit measurements. The choices of bases for these measurements as well as the structure of the entanglements specify a quantum algorithm. The needed computations i...

In one-way quantum computations (1WQC), quantum correlations in an entangled state, called a cluster or graph state, are exploited to perform universal quantum computations using single-qubit measurements. The choices of bases for these measurements as well as the structure of the entanglements specify a quantum algorithm. The needed computations i...

Designing with field-programmable gate arrays (FPGAs) can face with difficulties due to process variations. Some techniques use reconfigurability of FPGAs to reduce the effects of process variations in these chips. Furthermore, FPGA architecture enhancement is an effective way to degrade the impact of variation. In this paper, various FPGA architec...

One of the major challenges in the process of three-dimensional integrated circuit fabrication is the manufacturing of through silicon vias (TSV). These TSVs compared with other connection elements require high manufacturing costs as well as large silicon area. In this paper, replication technique has been used to reduce the number of TSVs in 3D FP...

In high frequency FPGAs with technology scale shrinking and threshold voltage value decreasing and based on existing large numbers of unused resources, leakage power has a considerable contribution in total power consumption. On the other hand, process variation, as an important challenge in nano-scale technologies, has a great impact on leakage po...

Leakage power in nano-scale technologies is an important source of power consumption. Moreover, FP-GAs with low utilization rates consume large leakage power in their routing and logical resources. As FPGA routing architecture incorporates large number of transistors, leakage power of routing resources contributes the majority of total leakage powe...

Quantum circuit design flow consists of two main tasks: synthesis and physical design. Addressing the limitations imposed
on optimization of the quantum circuit objectives because of no information sharing between synthesis and physical design
processes, we introduced the concept of “physical synthesis” for quantum circuit flow and proposed a techn...

Interconnect mis-prediction is a major problem in nano-scale design that may diminish the quality of physical design algorithms or may even result in design divergence. In this paper, a new interconnect-planning methodology based on assume and enforce strategy is presented. In this methodology, some regions of the chip are planned to provide auxili...

This paper proposes a new switch box architecture in SRAM-based FPGAs to mitigate soft errors. In this switch box architecture, the number of SRAM bits required for programming the switch box is reduced to 67% without any impact on routing capability of the switch box. This architecture does not require any modification of the existing placement an...

Uncertainty in performance of FPGAs is becoming an important issue due to increased process variations in nanometer regime. Therefore, it is vital to decrease the impact of variability in these devices. FPGA routing architecture enhancement can be an effective way, because as feature size scales down, routing delay dominates logic circuit delay. In...

In this paper, the problem of constructing an efficient quantum circuit for
the implementation of an arbitrary quantum computation is addressed. To this
end, a basic block based on the cosine-sine decomposition method is suggested
which contains $l$ qubits. In addition, a previously proposed quantum-logic
synthesis method based on quantum Shannon d...

SRAM-based FPGAs suffer from soft errors caused by cosmic particles. This paper introduces a new switch box architecture to mitigate soft errors. In this switch box architecture, the number of SRAM bits required for programming the switch boxes is reduced by means of switch reduction with slight impact on routing capability of the switch box. This...

In recent years, parameter variations present critical challenges for manufacturability and yield on integrated circuits. In this paper, a new method for improving the timing yield of field programmable gate array (FPGA) devices affected by random and systematic within-die variation is proposed. By selection of an appropriate configuration from a s...

Mis-prediction is a dominant problem in nano-scale design that may diminish the quality of physical design algorithms or may even result in failing the design cycle convergence. In this paper, a new planning methodology is presented in which a masterplan of the chip is constructed in early levels of physical design and the rest of succeeding physic...

Buffer insertion plays an important role in circuit performance and signal integrity especially in deep submicron technologies. The stage at which buffers are inserted in a design has a large impact on the design quality. Early buffer insertion may cause misestimation due to unknown cell locations whereas buffer insertion after placement may not be...

The signal integrity problem, especially crosstalk noise, is an important issue in physical design in the nanometer regime. Wire multiplexing is a recently proposed method to reduce these problems in current design methodologies. This technique is presented to increase the routability of the design and also reduce crosstalk noise by serializing par...

Reversible logic has applications in various research areas including signal
processing, cryptography and quantum computation. In this paper, direct
NCT-based synthesis of a given $k$-cycle in a cycle-based synthesis scenario is
examined. To this end, a set of seven building blocks is proposed that reveals
the potential of direct synthesis of a giv...

Synthesis of reversible logic has received significant attention in the recent years and many synthesis approaches for reversible circuits have been proposed so far. In this paper, a library-based synthesis methodology for reversible circuits is proposed where a reversible specification is considered as a permutation comprising a set of cycles. To...

Reversible logic has applications in various research areas including
low-power design and quantum computation. In this paper, a rule-based
optimization approach for reversible circuits is proposed which uses both
negative and positive control Toffoli gates during the optimization. To this
end, a set of rules for removing NOT gates and optimizing s...

Quantum circuit design flow consists of two main tasks: synthesis and physical design. In the current flows, two procedures are performed subsequently and without any information sharing between two processes that can limit the optimization of the quantum circuit metrics; synthesis converts the design description into a technology-dependent netlist...

This paper proposes a new switch box architecture in SRAM-based FPGAs to mitigate soft error effects. In this switch box architecture, the number of SRAM bits required for programming switch box is reduced to 67% without any impact on routing capability of the switch box. This architecture does not require any modification of the existing placement...

3D technology is an attractive solution for reducing wirelength in a field programmable gate array (FPGA). However, trough silicon vias (TSV) are limited in number. In this paper, we propose a tilable switch module architecture based on the 3D disjoint switch module for 3D FPGAs. Experimental results over 20 MCNC benchmarks show 62% reduction in th...

Quantum circuit design flow consists of two main tasks: synthesis and physical design. In the current flows, two procedures are performed subsequently; synthesis converts the design description into a technology-dependent netlist and then physical design takes the fixed netlist, produces layout, and schedules the netlist on the layout. This style o...

Multi-domain clock skew scheduling is a cost effective technique for performance improvement. However, the required wire length and area overhead due to phase shifters for realizing such clock scheduler may be considerable if registers are placed without considering assigned skews. Focusing on this issue, in this paper, we propose a skew scheduling...

Mis-prediction is a dominant problem in nano-scale design that may diminish the quality of physical design algorithms or may even result in failing the design cycle convergence. In this paper, a new planning methodology is presented in which a masterplan of the chip is constructed in early levels of physical design and the rest of succeeding physic...

Several algorithms have been proposed for the synthesis of reversible circuits. In this paper, a cycle-based synthesis algorithm for reversible logic, based on the NCT library, has been proposed. In other words, direct implementation of a single 3-cycle, a pair of 3-cycles and a pair of 2-cycles have been explored and used to propose an efficient T...

In this paper, we propose a probabilistic method to estimate intra-grid wirelength of nets after placement or global routing.
Results of incorporating this method in the previous probabilistic coupling capacitance and crosstalk estimation scheme show
its efficiency in detecting noisy nets before having detailed information of wire adjacency. Our ge...

Reversible circuits have applications in various research areas including signal processing, cryptography and quantum computation. In this paper, a non-search based moving forward synthesis algorithm ( MOSAIC) for Boolean reversible circuits is proposed to convert an arbitrary well-formed matrix into an identity matrix using a set of reversible gat...

To improve the performance of embedded processors, an effective technique is collapsing critical computation subgraphs as
application-specific instruction set extensions and executing them on custom functional units. The problem with this approach
is the immense cost and the long times required to design a new processor for each application. As a s...

With today’s networks complexity, routers in backbone links must be able to handle millions of packets per second on each of their ports. Determining the corresponding output interface for each incoming packet based on its destination address requires a longest matching prefix search on the IP address. Therefore, IP address lookup is one of the mos...

Due to the increasing number of elements on a single chip area and the growing complexity of routing, existing methods to reduce crosstalk at the routing or post-routing stage do not seem efficient anymore. So crosstalk estimation should be considered in earlier design stages such as placement. To estimate crosstalk after placement information abou...

Routability, signal integrity and manufacturability are important issues in physical design and congestion reduction is a widely used method for ameliorating these problems in current design methodologies. Besides, routing congestion may create large delays in detoured global wires that can be avoided by congestion reduction. In recent years, async...

In this paper, a probabilistic method is introduced to estimate intra-grid wirelength of nets after placement and global routing. In addition, a crosstalk reduction scheme is proposed based on our estimations and a resultant crosstalk map. Our wirelength estimations incorporated with the previous crosstalk estimation schemes, efficiently detect fai...

It can be shown that if quantum algorithms run on quantum computers, their processing speeds improve exponentially compared to their classical counterparts. However, due to the lack of quantum computers circuit model of quantum algorithms are currently simulated using classical computers to verify their functionalities. On the other hand, software...