Mohammed F. Tolba

Khalifa University | KU

In the world of deep learning, Transformer models have become very significant, leading to improvements in many areas from understanding language to recognizing images, covering a wide range of applications. Despite their success, the deployment of these models in real-time applications, particularly on edge devices, poses significant challenges du...

The challenges of Convolutional neural networks (CNNs) based AI inference on edge devices include computing complexity, large memory requirements, and high power consumption. Researchers have pursued efficient hardware, dataflow optimization, and new algorithms to tackle these obstacles. This paper introduced a novel acceleration methodology design...

Deep Neural Networks (DNNs) are computationally and memory intensive, which present a big challenge for hardware, especially for resource-constrained devices such as Internet-of-Things (IoT) nodes. This paper introduces a new method to improve DNNs performance by fusing approximate computing with data reuse techniques for image recognition applicat...

This paper presents a novel cross-coupling capacitor processing unit (C3PU) that supports analog-mixed signal in-memory computing to perform multiply-and-accumulate (MAC) operations. The C3PU consists of a capacitive unit, a CMOS transistor, and a voltage-to-time converter (VTC). The capacitive unit serves as a computational element that holds the...

This paper presents a novel cross-coupling capacitor processing unit (C3PU) that supports analog-mixed signal in memory computing to perform multiply-and-accumulate (MAC) operations. The C3PU consists of a capacitive unit, a CMOS transistor, and a voltage-to-time converter (VTC). The capacitive unit serves as a computational element that holds the...

This paper proposes an efficient encryption technique based on Dynamic and Secure Substitution Box (DS2B) design suitable for IoT and resource-constrained platforms. The DS2B has the advantages of simple structure and good encryption performance. A different number of strong S-boxes could be generated with minor variations in the DS2B parameters. P...

Deep Neural Networks (DNNs) are computationally and memory intensive, which makes their hardware implementation a challenging task especially for resource constrained devices such as IoT nodes. To address this challenge, this paper introduces a new method to improve DNNs performance by fusing approximate computing with data reuse techniques to be u...

This paper presents a secure and efficient substitution box (s-box) for speech encryption applications. The proposed s-box data changes every clock cycle to swap the input signal with different data, where it generated based on a new algorithm and a memristor chaotic system. Bifurcation diagrams for all memristor chaotic system parameters are intro...

This paper presents a multi-mode generalized modified transition chaotic map and a switched chaotic encryption scheme based on it. Eight different modes of operation can be selected based on the map graph (concave or convex), the range modification procedure (shrinking or widening) and the sign of one of its independent parameters. The generalizati...

This paper introduces a study for the effect of using different floating-point representations on the chaotic system’s behaviour. Also, it offers a comparison between the attractors at three different orders, (integer, fractional, and mixed-order). This comparison shows the minimum number of bits needed for all parameters to simulate the chaotic at...

Binary convolutional neural networks (BCNN) have been proposed in the literature for resource-constrained IoTs nodes and mobile computing devices. Such computing platforms have strict constraints on the power budget, system performance, processing and memory capabilities. Nonetheless, the platforms are still required to efficiently perform classifi...

We propose a mathematical system capable of exhibiting chaos with a chaotic attractor which is odd symmetrical in the x − y phase plane but even symmetrical in the x − z and y − z phase planes respectively. A hardware implementation of the system is done on a digital FPGA platform for verification. The system is also attractive in the sense that (i...

This paper introduces an intensive discussion for the dynamical model of the love triangle in both integer and fractional-order domains. Three different types of nonlinearities soft, hard, and mixed between soft and hard, are used in this study. MATLAB numerical simulations for the different three categories are presented. Also, a discussion for ho...

The efficiency of the hardware implementations of fractional-order systems heavily relies on the efficiency of realizing the fractional-order derivative operator. In this work, a generic hardware implementation of the fractional-order derivative based on the Grünwald–Letnikov’s approximation is proposed and verified on a field-programmable gate arr...

Chaotic systems have remarkable importance in capturing some complex features of the physical process. Recently, fractional calculus becomes a vigorous tool in characterizing the dynamics of complex systems. The fractional-order chaotic systems increase the chaotic behavior in new dimensions and add extra degrees of freedom, which increase system c...

Memristor characteristics such as nonlinear dynamics, state retention and accumulation are useful for many applications. FPGA implementation of memristor-based systems and algorithms provides fast development and verification platform. In this work, we first propose a versatile digital memristor emulator that exhibits either continuous or discrete...

This paper proposes a new fractional-order multi-scrolls chaotic system. More complex systems and flexible ranges of the chaotic behavior are obtained due to the extra parameters added by the fractional-order. The proposed system has novel complex chaotic behaviors. The effect of changing the system parameters on the system behavior is investigated...

Exploring the implementation of fractional calculus is essential to be adequately used in several applications. This paper introduces an FPGA design methodology of fractional order multi-scrolls chaotic system. Hardware resources comparison proves the efficiency of the proposed method. The designs are simulated using Xilinx ISE 14.7 and realized on...

This paper proposes a generalized modified chaotic transition map with three independent parameters. A hardware speech encryption scheme utilizing this map along with a bit permutation network is presented. While the transition map’s generalization introduces additional parameters, the modification enhances its chaotic properties and overcomes the...

This paper generalizes the Izhikevich neuron model in the fractional-order domain for better modeling of neuron dynamics. Accurate and computationally efficient numerical techniques such as non-standard finite difference (NSFD) scheme is used to solve the neuron system in the fractional-order domain for different cases. Neuron synchronization plays...

This paper introduces design and FPGA implementation of sound encryption system based on a fractional-order chaotic system. Also, it presents the FPGA implementation of Tang, Yalcin, and Özoǧuz fractional order chaotic systems. The Grunwald-Letnikov (GL) definition is used to generalize the investigated systems into the fractional-order domain. Als...

Exploring the use of fractional calculus is essential for it to be used properly in various applications. Implementing the fractional operator $D^α$ in FPGA is an important research topic in fractional calculus; in the literature, only a few FPGA implementations have been proposed due to the memory dependence of the fractional order systems. In thi...

Exploring the nonlinear dynamics of the memristors is essential to be adequately used in the applications. Realizing memristor on FPGAs as an Intellectual Property (IP) core offers a flexible platform to realize different models. In the literature, few implementations have been proposed for simple and limited memristor model. In this brief, two dis...

This paper proposes a hardware platform implementation on FPGA for two fractional-order derivative operators. The Grünwald-Letnikov and Caputo definitions are realized for different fractional orders. The realization is based on non-uniform segmentation algorithm with a variable lookup table. A generic implementation for Grünwald-Letnikov is propos...

This paper discusses the FPGA implementation of the fractional-order derivative as well as two fractional-order chaotic systems where one of them has controllable multi-scroll attractors. The complete hardware architecture of the Grünwald-Letnikov (GL) differ-integral is realized with different memory window sizes. As an application of the proposed...

A fixed-point ASIC design for high-speed, second-order, piecewise function approximation is presented. A Non-Uniform segmentation method based on Minimax approximation is used to get the interpolation coefficients. Non-Uniform segmentation, effectively, reduces the size of the coefficient table with a small area overhead for the address encoder. Th...