Mihai Teodor Lazarescu

Mihai Teodor Lazarescu
Politecnico di Torino | polito · DET - Department of Electronics and Telecommunications

PhD

About

74
Publications
33,261
Reads
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1,236
Citations
Citations since 2017
27 Research Items
847 Citations
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2017201820192020202120222023050100150
2017201820192020202120222023050100150
Introduction
Special Issue on “Real-Time Sensor Networks and Systems for the Industrial IoT”. Deadline January 31, 2020, https://www.mdpi.com/journal/sensors/special_issues/industrial_IoT MDPI Sensors journal (SCOPUS IF 3.0). Accepted submissions will be published in the journal as soon as accepted after peer-review. Dr. Christos Koulamas, Dr. Mihai Teodor Lazarescu, Guest Editors
Additional affiliations
December 2011 - present
Politecnico di Torino
Position
  • Research Assistant
July 2000 - October 2002
Cadence Design Systems, Inc.
Position
  • Engineer
Description
  • Embedded software execution performance estimation tool for the Virtua Component Co-design (VCC) project.

Publications

Publications (74)
Article
Full-text available
Long-term wildfire monitoring using distributed in situ temperature sensors is an accurate, yet demanding environmental monitoring application, which requires long-life, low-maintenance, low-cost sensors and a simple, fast, error-proof deployment procedure. We present in this paper the most important design considerations and optimizations of all e...
Article
Full-text available
The Internet of Things (IoT) provides a virtual view, via the Internet Protocol, to a huge variety of real life objects, ranging from a car, to a teacup, to a building, to trees in a forest. Its appeal is the ubiquitous generalized access to the status and location of any "thing" we may be interested in. Wireless sensor networks (WSN) are well suit...
Article
Full-text available
Capacitive sensing at long ranges (10x the plate diameter) for long-term environmental monitoring can be limited by slow but significant measurement drifts from charge induction, which can exceed the small capacitance variations of interest, below 0.01%. This paper proposes a slope modulation differential capacitance measurement method for single-p...
Article
Full-text available
Designs implemented on field-programmable gate arrays (FPGAs) via high-level synthesis (HLS) suffer from off-chip memory latency and bandwidth bottlenecks. FPGAs can access both large but slow off-chip memories (DRAM), and fast but small on-chip memories (block RAMs and registers). HLS tools allow exploiting the memory hierarchy in a scratchpad-lik...
Article
Full-text available
The channel model is by far the most computing intensive part of the link level simulations of multiple-input and multiple-output (MIMO) fifth-generation new radio (5G NR) communication systems. Simulation effort further increases when using more realistic geometry-based channel models, such as the three-dimensional spatial channel model (3D-SCM)....
Article
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Platforms with multiple Field Programmable Gate Arrays (FPGAs), such as Amazon Web Services (AWS) F1 instances, can efficiently accelerate multi-kernel pipelined applications, e.g., Convolutional Neural Networks for machine vision tasks or transformer networks for Natural Language Processing tasks. To reduce energy consumption when the FPGAs are un...
Article
Full-text available
Ever since transistor cost stopped decreasing, customized programmable platforms, such as field-programmable gate arrays (FPGAs), became a major way to improve software execution performance and energy consumption. While software developers can use high-level synthesis (HLS) to speed up register-transfer level (RTL) code generation from C++ or Open...
Article
Full-text available
Indoor localization has many pervasive applications, like energy management, health monitoring, and security. Tagless localization detects directly the human body, like passive infrared sensing, and is the most amenable to different users and use cases. We evaluate the localization and tracking performance, as well as resource and processing requir...
Article
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Wireless sensor networks find extensive applications, such as environmental and smart city monitoring, structural health, and target location. To be useful, most sensor data must be localized. We propose a node localization technique based on bilateration comparison (BACL) for dense networks, which considers two reference nodes to determine the unk...
Article
Full-text available
To increase railway use efficiency, the European Railway Traffic Management System (ERTMS) Level 3 requires all trains to constantly and reliably self-monitor and report their integrity and track position without infrastructure support. Timely train separation detection is challenging, especially for long freight trains without electrical power on...
Article
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The Industrial Internet of Things (Industrial IoT-IIoT) is the emerging core backbone construct for the various cyber-physical systems constituting one of the principal dimensions of the 4th Industrial Revolution [...].
Article
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Low cost, ubiquitous, tagless, and privacy aware indoor monitoring is essential to many existing or future applications, such as assisted living of elderly persons. We explore how well different types of neural networks in basic configurations can extract location and movement information from noisy experimental data (with both high-pitch and slow...
Article
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The continuous growth of modern cities and the request for better quality of life, coupled with the increased availability of computing resources, lead to an increased attention to smart city services. Smart cities promise to deliver a better life to their inhabitants while simultaneously reducing resource requirements and pollution. They are thus...
Article
Full-text available
Multi-FPGA platforms like Amazon Web Services F1 are perfect to accelerate multi-kernel pipelined applications, like Convolutional Neural Networks (CNNs). To reduce energy consumption, we propose to upload at runtime the best power-optimized CNN implementation for a given throughput constraint. Our design method gives the best number of parallel in...
Article
Full-text available
Multi-FPGA platforms, like Amazon AWS F1, can run in the cloud multi-kernel pipelined applications, like Convolutional Neural Networks (CNNs), with excellent performance and lower energy consumption than CPUs or GPUs. We propose a method to efficiently map these applications on multi-FPGA platforms to maximize the application throughput. Our method...
Preprint
Full-text available
Using capacitive sensors at long ranges (10-20x their plate diameter) for long term environmental sensing can be limited by slow but significant measurement drifts that can often far exceed the small capacitance variations of interest, which can be around 0.01% or less. We propose a differential capacitance measurement method that rejects the quasi...
Conference Paper
Full-text available
Many applications aim to make smarter the indoor environments where most people spend much of their time (home, office, transportation, public spaces), but they need long-term low-cost human sensing and monitoring capabilities. Small capacitive sensors match well most requirements, like privacy, power, cost, and unobtrusiveness, and, importantly, t...
Article
Full-text available
Human detection, identification, and monitoring is essential for many applications aiming to make smarter the indoor environments, where most people spend much of their time (like home, office, transportation, or public spaces). Capacitive sensors can meet stringent privacy, power, cost, unobtrusiveness requirements, they do not rely on wearables o...
Conference Paper
Full-text available
FPGA-based accelerators demonstrated high energy efficiency compared to GPUs and CPUs. However, single FPGA designs may not achieve sufficient task parallelism. In this work, we optimize the mapping of high-performance multi-kernel applications, like Convolutional Neural Networks, to multi-FPGA platforms. First, we formulate the system level optimi...
Article
Full-text available
Although useful for many applications, the practical use of tagless remote human identification is often hampered by privacy, usability, reliability, or cost concerns. In this paper, we explore the use of capacitive sensors, which appear to address most of these concerns, to identify different persons based on the unique electric and dielectric pro...
Chapter
Versatile and effective, Wireless Sensor Networks (WSNs) witness a continuous expansion of their application domains. Yet, their use is still hindered by issues such as reliability, lifetime, overall cost, design effort and multidisciplinary engineering knowledge, which often prove to be daunting for application domain experts. Several WSN design m...
Article
Full-text available
Using FPGA-based acceleration of High- Performance Computing (HPC) applications to reduce energy and power consumption is becoming an interesting option, thanks to the availability of High-Level Synthesis (HLS) tools that enable fast design cycles. However, obtaining good performance for memory-intensive algorithms, which often exchange large data...
Chapter
Full-text available
Wireless sensor networks (WSN) are recognized key enablers for the Internet of Things (IoT) paradigm since its inception. WSNs are a resilient and effective distributed data collection technology, but issues related to reliability, autonomy, cost, and accessibility to application domain experts still limit their wide scale use. Commercial solutions...
Article
Full-text available
Accurate tagless indoor person localization is important for several applications, such as assisted living and health monitoring. Machine learning classifiers can effectively mitigate sensor data variability and noise due to deployment-specific environmental conditions. In this study, we use experimental data from a capacitive sensor-based indoor h...
Chapter
Versatile and effective, Wireless Sensor Networks (WSNs) witness a continuous expansion of their application domains. Yet, their use is still hindered by issues such as reliability, lifetime, overall cost, design effort and multidisciplinary engineering knowledge, which often prove to be daunting for application domain experts. Several WSN design m...
Article
Full-text available
High-level Synthesis (HLS) based design methodologies are extremely viable for industries that are sensitive to production costs. In order to have competitive advantage, the ability to have several different implementations of the same algorithm satisfying a diverse range of resolution, cost and performance constraints is highly desirable. In this...
Article
Full-text available
Accurate indoor person localization is essential for several services, such as assisted living. We introduce a tagless indoor person localization system based on capacitive sensing and localization algorithms that can determine the location with less than 0.2 m average error in a 3 m × 3 m room and has recall and precision better than 70%. We also...
Article
Full-text available
In this article we present the main results obtained in the ARTEMIS-JU WSN-DPCM project between October 2011 and September 2015. The first objective of the project was the development of an integrated toolset for Wireless sensor networks (WSN) application planning, development, commissioning and maintenance, which aims to support application domain...
Article
Full-text available
Massive amounts of legacy sequential code need to be parallelized to make better use of modern multiprocessor architectures. Nevertheless, writing parallel programs is still a difficult task. Automated parallelization methods can be effective both at the statement and loop levels and, recently, at the task level, but they are still restricted to sp...
Article
Full-text available
Multicore architectures are increasingly used in embedded systems to achieve higher throughput with lower energy consumption. This trend accentuates the need to convert existing sequential code to effectively exploit the resources of these architectures. We present a parallelization flow and toolset for legacy C code that includes a performance est...
Article
Full-text available
Networked embedded systems are essential building blocks of a broad variety of distributed applications ranging from agriculture to industrial automation to healthcare and more. These often require specific energy optimizations to increase the battery lifetime or to operate using energy harvested from the environment. Since a dominant portion of po...
Chapter
The Internet of Things (IoT) provides a virtual view, via the Internet Protocol, to a huge variety of real life objects, ranging from a car, to a teacup, to a building, to trees in a forest. Its appeal is the ubiquitous generalized access to the status and location of any “thing” we may be interested in. Wireless sensor networks (WSN) are well suit...
Chapter
Full-text available
Wireless Sensor Networks (WSN)-based data gathering solutions were envisioned from the beginning of the Internet of Things (IoT) paradigm because of their important characteristics such as low-cost, long-term versatile sensing and actuation capabilities, and distributed resilient bidirectional communications. However, many technologies converge int...
Article
Full-text available
Writing parallel code is difficult, especially when starting from a sequential reference implementation. Our research efforts, as demonstrated in this paper, face this challenge directly by providing an innovative toolset that helps software developers profile and parallelize an existing sequential implementation, by exploiting top-level pipeline-s...
Conference Paper
Full-text available
In this article, we present the work-in-progress of the EU FP7 PHARAON project, started in September 2011. The first objective of the project is the development of new techniques and tools capable to assist the designer in the development of parallel embedded systems, from executable specifications to target-specific implementation and debugging on...
Conference Paper
Full-text available
The paper presents the design and multi-parameter optimization of a networked embedded application for the healthcare domain. Several hardware, software, and application parameters, such as clock frequency, sensor sampling rate, data packet rate, are tuned at design- and run-time according to application specifications and operating conditions to o...
Conference Paper
Full-text available
Using FPGAs as hardware accelerators that communicate with a central CPU is becoming a common practice in the embedded design world but there is no standard methodology and toolset to facilitate this path yet. On the other hand, languages such as CUDA and OpenCL provide standard development environments for Graphical Processing Unit (GPU) programmi...
Conference Paper
Full-text available
Writing parallel code is difficult, especially when starting from a sequential reference implementation. Our research efforts, as demonstrated in this paper, face this challenge directly by providing an innovative toolset that helps software developers profile and parallelize an existing sequential implementation, by exploiting top-level pipeline-s...
Conference Paper
Full-text available
Writing parallel code is traditionally considered a difficult task, even when it is tackled from the beginning of a project. In this paper, we demonstrate an innovative toolset that faces this challenge directly. It provides the software developers with profile data and directs them to possible top-level, pipeline-style parallelization opportunitie...
Conference Paper
Full-text available
Verification and design-space exploration of today's embedded systems require the simulation of heterogeneous aspects of the system, i.e., software, hardware, communications. This work shows the use of SystemC to simulate a model-driven specification of the behavior of a networked embedded system together with a complete network scenario consisting...
Conference Paper
Full-text available
This paper describes several optimizations of MAC protocols that can be applied in order to satisfy the constraints that come from a real-life application. Forest fire monitoring requires very different latencies and data sizes, depending on whether it is reporting normal conditions, sending an alarm, or performing network management functions. We...
Patent
Full-text available
Systems and methods are provided for annotating software with performance information. The computer code is compiled into assembler code, the assembler code is translated into a simulation model, expressed in assembler-level source code. The simulation model is annotated with information for calculating various performance parameters of the softwar...
Article
Full-text available
This paper presents our industrial experience on the implementation of Minteos Mesh Protocol which is a memory, power and delay efficient mesh protocol; and Minteos SystemC Simulator for mesh networks. Experiments are carried out to validate the adequate use of Minteos Mesh Protocol. Also, simulation/test results are given to show the effectiveness...
Conference Paper
Full-text available
Modern embedded systems must execute a variety of high performance real-time tasks, such as audio and image compression and decompression, channel coding and encoding, etc. High hardware design and mask production costs dictate the need to re-use an architectural platform for as many applications as possible. Reconfigurable platforms can be very ef...
Article
Full-text available
High-level cost and performance estimation, coupled with a fast hardware/software co-simulation framework, is a key enabler to a fast embedded system design cycle. Unfortunately, the problem of deriving such estimates without a detailed implementation available is very difficult.
Article
Full-text available
High-level cost and performance estimation, coupled with a fast hardware/software co-simulation framework, is a key enabler to a fast embedded system design cycle. Unfortunately, the problem of deriving such estimates without a detailed implementation available is difficult. In this paper we describe two approaches to solve software cost and perfor...
Conference Paper
Full-text available
In this paper a new approach to operation scheduling and binding in asynchronous High Level Synthesis (HLS) is presented. We developed a genetic algorithm and integrated it inside Pipefitter, an existing tool for the automated synthesis of asynchronous circuit. A Control Data Flow Graph (CDFG), derived by Pipefitter from an HDL specification, is th...
Conference Paper
Full-text available
Scheduling is widely recognized as a very important step in high-level synthesis. Nevertheless, it is usually done without taking into account the effects on the actual hardware implementation. This paper presents an efficient symbolic technique to concurrently integrate operation scheduling and resource allocation. The technique inherits all the f...
Article
Full-text available
Scheduling is widely recognized as a very important step in high-level synthesis. Nevertheless, it is usually done without taking into account the effects on the actual hardware implementation. This paper presents an efficient symbolic technique to concurrently integrate operation scheduling and resource allocation. The technique inherits all the f...
Conference Paper
Full-text available
High-level cost and performance estimation, coupled with a fast hardware/software co-simulation framework, is a key enabler to a fast embedded system design cycle. Unfortunately, the problem of deriving such estimates without a detailed implementation available is difficult. In this paper we describe two approaches to solve software cost and perfor...
Conference Paper
Full-text available
The paper addresses embedded software performance estimation. Known approaches use either behavioral simulation with timing annotations, or a clock cycle-accurate model of instruction execution (e.g., an instruction set simulator). We propose a hybrid approach, that features both the high simulation speed and flexibility from the former approach an...
Conference Paper
Full-text available
High-level cost and performance estimation, coupled with a fast hardware/software co-simulation framework, is a key enabler to a fast embedded system design cycle. Unfortunately, the problem of deriving such estimates without a detailed implementation available is very difficult. In this paper we focus on embedded software performance estimation. C...
Conference Paper
Full-text available
In this paper we will describe a modality to speed up the design of the VLSI digital (mainly DSP) circuits and to reduce the design errors by increasing the interaction between the ad-hoc software program developed to validate the algorithm and the VHDL description and simulation. A real case of a digital power analyzer will be used for exemplifica...
Conference Paper
Full-text available
This paper describes an eecient implementation of a power supply meter. The implementation is based on the Fourier series decomposition algorithm, using CORDIC algorithm for complex mathematical computations. It is able to calculate RMS and peak values, phase shift, power factor, and complex, active, and reactive power for two periodic waveforms up...
Conference Paper
Full-text available
In this paper are described some of the issues of the mixed signal standard cell VLSI design with emphasis on the practical experience resulted from designing a carrier transceiver in SGS-THOMSON 2 μm BiCMOS technology. Presented are the circuit block structure, some advantages and disadvantages of the standard cell design approach, the testing str...
Conference Paper
Full-text available