Meisam Abdollahi

University of Victoria | UVIC · Electrical and Computer Enginering

Background: Large Language Models (LLMs) are emerging as promising tools in hardware design and verification, with recent advancements suggesting they could fundamentally reshape conventional practices. Objective: This study examines the significance of LLMs in shaping the future of hardware design and verification. It offers an extensive literatur...

Large Language Models (LLMs) are emerging as promising tools in hardware design and verification, with recent advancements suggesting they could fundamentally reshape conventional practices. In this survey, we analyze over 54 research papers to assess the current role of LLMs in enhancing automation, optimization, and innovation within hardware des...

Dear Colleagues, We cordially invite you to submit your papers for the MDPI Electronics (IF=2.9) special issue on "Machine Learning in Network-on-Chip (NoC) Architectures". The goal of this special issue is to explore the intersection of machine learning and NoC architectures and present the latest advancements, applications, and challenges as the...

In many Internet of Things (IoT) applications, knowing the device's location can be quite important for some reasons such as asset tracking and inventory management, geolocation services, safety and security, environmental monitoring, and proximity-based interactions. Mobile users often experience mobile services/applications within an indoor or ou...

Optical Network on Chip (ONoC) is now considered a promising alternative to traditional electrical interconnects. Meanwhile, several challenges such as temperature and process variations, aging, crosstalk noise, and insertion loss endanger the data transmission reliability of ONoCs. Many investigations have been made to evaluate the effect of these...

Nanophotonics as a promising candidate for future on-chip networks has several benefits such as bandwidth transparency, light-speed data rate and low power consumption. Despite significant features of optical on-chip data transmission, the challenges of thermal and process variations (PVs) threaten the photonic network-on-chip reliability. These va...

Nowadays, static power consumption in chip multiprocessor (CMP) is the most crucial concern of chip designers. Power-gating is an effective approach to mitigate static power consumption particularly in low utilization. Network-on-Chip (NoC) as the backbone of multi- and many-core chips has no exception. Previous state-of-the-art techniques in power...

Crosstalk and insertion loss are the crucial determinants of ring resonated routers. A novel 2 × 2 optical switch is proposed through a combination of broadband waveguide crossing and X-shape photonic crystal ring resonators. The main goal of the proposed design is to demonstrate the switching wavelengths based on changing the refractive index and...

Nanophotonic is considered an emerging technology for future many-core systems due to its potentials for low-power and high-bandwidth communications. Nevertheless, challenges such as crosstalk noise and temperature variation of photonic devices significantly reduce the optical signal-to-noise ratio which leads to reliability decrease in the optical...

Multi/Many-core systems based on the traditional electrical network-on-chip are confronted with the limited bandwidth, high latency, and reliability challenges. The emerging optical solution of silicon photonics has promised to improve the design parameters of electrical interconnections for future multiprocessor system on chips. Although the optic...

Applying power gating on network-on-chip (NoC) as an effective static power-aware technique could lead to a significant reduction in on-chip network performance. Since the NoC performance has a considerable impact on the overall chip performance, providing a trade-off between chip power and its performance is crucial. To this end, applying power ga...

This paper proposes a novel topology for optical Network on Chip (NoC) architectures with the key advantages of regularity, vertex symmetry, scalability to large scale networks, constant node degree, and simplicity. Moreover, we propose a minimal deterministic routing algorithm for the proposed topology which leads to small and simple photonic rout...

This paper proposes a nanophotonic Network-on-Chip architecture based on the traditional Cube-Connected Cycles topology (CCC), which is named as ONC 3. We also suggest a contention-free quasi-Dimension-Order-Routing algorithm for the proposed structure. Compared to the previous 2D layouts, our novel scheme lessens the crosstalk parameter of the ins...

This article proposes a Semi Online Reliable Task (SORT) mapping approach to many-core platforms divided into two sections: offline and online. The offline section is a twofolded approach. It maintains the reliability of the mapped task graph against soft errors considering the reliability threshold defined by designers. As wear-out mechanisms decr...

This article presents a new reliability-aware task mapping approach in a many-core platform at design time for applications with DAG-based task graphs. The main goal is to devise a task mapping which meets a predefined reliability threshold considering a minimized performance degradation. The proposed approach uses a majority-voting replication tec...

This paper proposes a model for a new reliability-aware task scheduling method for hard real-time multi-core systems. The proposed method is based on a novel clustered replication which maintains the desired reliability threshold, minimizing both inter-core communication and redundancy overhead in multi-core network-on-chip based platforms. Both si...

Standby-sparing is one of the common techniques in order to design fault-tolerant safety-critical systems where the high level of reliability is needed. Recently, the minimization of energy consumption in embedded systems has attracted a lot of concerns. Simultaneous considering of high reliability and low energy consumption by DVS is a challenging...