Matheus Alcântara Souza

Pontifical Catholic University of Minas Gerais | PUC-Minas · Departamento de Ciência da Computação

High-performance computing (HPC) systems need to handle ever-increasing data sizes for fast processing and quick response times. However, modern processors’ caches are unable to handle massive amounts of data, leading to significant cache miss penalties that affect performance. In this context, selecting an effective cache replacement policy is cru...

Along with the necessity of more computational power, CPUs are evolving quickly. Companies are developing new generations of CPUs every 1-2 years, and many options compete for market share. Hence, researchers and companies must develop a method to compare and select the best processor that fits their needs. This paper presents a simulation-driven a...

The rapid development of Quantum Computing (QC) as a promising computing paradigm has garnered significant attention for its ability to harness quantum mechanical properties for computation. With classical computing facing limitations outlined by Moore's Law, QC emerges as a potential alternative for tackling complex computational problems. Yet, to...

Machine Learning applications have their viability strongly linked to the ability of computer architectures to offer high performance and energy efficiency. Although different architectures can offer high computational performance, they may lack energy efficiency, which is crucial for consumer-based applications. For instance, Intrusion Detection S...

Algorithms for the extraction of formal concepts are widely studied in several areas of knowledge, such as finance, health, and statistics. However, these algorithms require high‐performance processing due to their combinatorial characteristics. In this work, an Open computing language (OpenCL)‐based Brute Force algorithm is proposed and evaluated...

Over the years, the amount of data shared between users from different areas have grown considerably. Consequently, so did network attacks. Security monitoring strategies must classify information types on networks quickly and effectively. Intrusion Detection Systems have been proposed with Machine Learning techniques and High-Performance Computing...

Algorithms for formal concept analysis are widely studied to extract computing intelligence patterns and knowledge discovery. However, they require high-performance processing due to their combinatorial characteristics. In this work, we design and evaluate a heterogeneous CPU+FPGA architecture to accelerate the concept extraction with large data se...

Due to their performance impact on program execution, cache replacement policies in set-associative caches have been studied in great depth. Currently, most general-purpose processors are multi-core, and among the very large corpus of research, and much to our surprise, we could not find any replacement policy that does actually take into account i...

Lightweight manycores deliver high performance and scal-ability at low power consumption. However, architectural intricacies of these processors impose programmability challenges that keep them away from mass adoption. While several efforts aim at introducing parallel programming environments to lightweight manycores, few initiatives are concerned...

FPGA devices have been proving to be good candidates to accelerate applications from different research topics. For instance, machine learning applications such as K-Means clustering usually relies on large amount of data to be processed, and, despite the performance offered by other architectures, FPGAs can offer better energy efficiency. With tha...

Performance of parallel scientific applications on many-core processor architectures is a challenge that increases every day, especially when energy efficiency is concerned. To achieve this, it is necessary to explore architectures with high processing power composed by a network-on-chip to integrate many processing cores and other components. In t...

A comunicação entre os núcleos de arquiteturas multi e many-corepode ser prejudicada se elas não adotarem estratégias apropriadas para interconexão. O uso das Networks-on-chip (NoCs) surge como alternativa, mitigando as limitações inerentes ao tamanho de barramentos e chaves crossbartradicionais. Porém, devem estar preparadas para lidar com diverso...

The use of multicore clusters is one of the strategies used to achieve energy-efficient multicore architecture designs. Even though chips have multiple cores in these designs, cache constraints such as size, latency, concurrency, and scalability still apply. Multicore clusters must therefore implement alternative solutions to the shared cache acces...

O crescimento constante no volume de bases de dados em variadas áreas de pesquisa tem demandado arquiteturas de computadores mais eficazes para a utilização de algoritmos de mineração de dados, de maneira a realizar análises eficientes dessas bases. Mais desempenho é necessário, e arquiteturas mais poderosas tendem a consumir mais energia, acrescen...

Data mining algorithms are essential tools to extract information from the increasing number of large datasets, also called BigData. However, these algorithms demand huge amounts of computing power to achieve reliable results. Although conventional High Performance Computing (HPC) platforms can deliver such performance, they are commonly expensive...

The constant need for faster and more energy-efficient processors has been stimulating the development of new architectures, such as low-power many-core architectures. Researchers aiming to study these architectures are challenged by peculiar characteristics of some components such as networks-on-chip and lack of specific tools to evaluate their pe...

One of the problems in Computer Science is the demand for more performance from the computer architectures. To surpass this problem, multi and many-core architectures can be used, which is a good strategy. These architectures must have an adequated interconnection system, in order to allow the communication between the diverse number of cores, whic...

The Networks-on-Chip approach is an alternative to achieve high-performance computing. In spite of using traditional interconnection systems, this strategy uses routers to enable the communication among the diverse cores in a many-core processor. However, with this approach, the processor performance may be compromised if the interconnection design...

A design challenge for multi-core processors is to obtain the best pos-sible level of energy efficiency. This paper presents results concerning the energy consumption of a simulated chip-multiprocessor architecture (CMP) with diffe-rent shared L2 cache models under different multi-threaded workloads. The decrease in cache size and its distribution...