Mark M. Budnik

Mark M. Budnik
Valparaiso University (USA) · Department of Electrical and Computer Engineering

About

27
Publications
1,446
Reads
How we measure 'reads'
A 'read' is counted each time someone views a publication summary (such as the title, abstract, and list of authors), clicks on a figure, or views or downloads the full-text. Learn more
79
Citations
Citations since 2017
0 Research Items
10 Citations
201720182019202020212022202301234
201720182019202020212022202301234
201720182019202020212022202301234
201720182019202020212022202301234

Publications

Publications (27)
Conference Paper
On behalf of the IEDEC Organizing Committee we would like to welcome you to the 4th Interdisciplinary Engineering Design & Education Conference (IEDEC 2014).
Conference Paper
On behalf of the ISQED 2013 conference and technical committees, we are pleased to welcome you to the 14th International Symposium on Quality Electronic Design, ISQED 2013. This conference is the premier multidisciplinary design and design automation conference, aimed at bridging the gap between and integration of, electronic design tools and proce...
Conference Paper
In 2004, The National Academy of Engineering released its seminal work, The Engineer of 2020 - Visions of Engineering in the New Century. The text attempts to prepare industrial, governmental, and academic institutions for the future of engineering. The report stated that an “Emphasis on the creative process will allow more effective leadership in...
Article
Valparaiso University engineering students have completed a service learning project to design and manufacture an upgraded braille printing press for Lutheran Braille Workers, Inc., a charitable organization that provides free-of-charge, Christian print material to visually impaired individuals around the world. There are approximately 314 million...
Chapter
We began by examining the properties and shortcomings of various parallel plate capacitors used in traditional integrated circuits. Based on these shortcomings, it is projected that MOSC and MIM devices will exhibit capacitances per unit area of less than 15fF/m2 by 2022. Therefore, because of their attractive properties, we investigated the feasib...
Conference Paper
Around the world, primary and secondary schools are challenged to implement appropriate programs for their gifted and talented students. In this paper, we present how our community's public school system and our college of engineering collaboratively developed and implemented a program on Nanotechnology for a group of forty 9-11 year olds on a comp...
Conference Paper
We introduce a vertical carbon nanotube capacitor with high capacitance per unit area. Using an electrical model of single-walled, metallic carbon nanotubes and the extracted capacitance values of a carbon nanotube bundle network, we develop an electrical model for the capacitor. The device can exhibit a capacitance greater than 175fF/mum<sup>2</su...
Conference Paper
We propose a new capacitor structure which uses carbon nanotube electrodes and is suitable for use in advanced integrated circuit technologies. Metallic carbon nanotubes have characteristics which make them well suited for capacitor electrodes (low resistance and large surface area per unit volume). We demonstrate that our thin vertical plate carbo...
Conference Paper
Full-text available
We demonstrate an integrated supply voltage variation suppression circuit for the reduction of di/dt event noise. The circuit was implemented in an 130 nm CMOS technology. For nominal conditions, the suppression circuit reduced the first droop supply voltage variation by 68.9%. The suppression circuit uses a digital control system which achieves a...
Conference Paper
Full-text available
We present electrical models for a carbon nanotube capacitor with high capacitance per unit area. We begin by introducing the concept of using vertically grown carbon nanotubes to develop a carbon nanotube capacitor. Three potential structures of the carbon nanotube capacitor are presented. We determine the capacitance per unit area for each struct...
Conference Paper
Full-text available
In this abstract, we present additional details on a new capacitor, CNCAP (carbon nanotube capacitor), compare it to existing integrated circuit capacitor technologies, and address its manufacturability. Properties of metallic, single wall CNTs (large surface area and relatively low resistance) allow for the creation of a very high density capacito...
Article
Full-text available
Abstract—All seniors in computer, electrical, and mechanical engineering at __________ University take a multidisciplinary senior design course. In the first week of the Fall semester, students are assigned to teams (based on their ranked preference), and each team is then given a project that contains both electrical and mechanical aspects. Some p...
Article
di/dt and IR events may cause large supply voltage variations and ohmic losses due to system parasitics. Today, decoupling capacitance is used to minimize the supply voltage variation, and parallelism in the power delivery path is used to reduce ohmic loss. Future integrated circuits, however, will exhibit large enough currents and current transien...
Conference Paper
In this paper we present a quantitative analysis of the use of metallic, single wall carbon nanotube (mSWCNT) bundles in future power delivery applications for nanoscale processors. We consider several factors which have been neglected in recent works (i.e. improvements in materials, limitations of nanotube packing density, increase of mSWCNT resis...
Conference Paper
IR events are periods in time when processors draw a high level of steady state operating current. During IR events, ohmic losses occur in the power delivery path. To minimize these ohmic losses, conventional systems use parallelism to reduce the resistance of the power delivery path. As operating currents continue to increase, however, additional...
Conference Paper
We present a novel application for carbon nanotube devices, implementing a high density 3-D capacitor, which can be useful for decoupling applications to reduce supply voltage variations. The capacitor consists of staggered layers of interleaved carbon nanotubes, alternately connected to anode and cathode contacts. The device can realize a capacita...
Conference Paper
IR and di/dt events may cause ohmic losses and large supply voltage variations due to system parasitics. Today, parallelism in the power delivery path is used to reduce ohmic loss while decoupling capacitance is used to minimize the supply voltage variation. Future integrated circuits, however, will exhibit large enough currents and current transie...
Conference Paper
Future nanoscale microprocessors may have integrated voltage regulators providing multiple supply voltages to meet their power and performance requirements. For their high input voltage, we have developed a model predicting the rate of dielectric breakdown of such regulators. Input parameters include oxide thickness, temperature, operating current,...
Conference Paper
In this work, a quad instrumentation amplifier was designed for optimum crosstalk reduction. The chip was designed for a multichannel data acquisition cardiac diagnostic system that requires high attenuation of the crosstalk between channels. Since the crosstalk problem was related to parasitic bipolar junction transistors between the inputs of the...
Article
Academic institutions are constantly looking for ways to improve the education of their engineering students. Training students to become productive engineers and leaders requires improvements in two fundamental areas: technical proficiency and communication skills. One of the best ways for students to improve both of these areas is to teach someon...
Article
Sparking scientific imagination in elementary students is an essential step in developing the engineers of the future. The curiosity to learn how things work while keeping an open mind to create new inventions forms the foundation of engineering. Over the past two summers, Valparaiso University's College of Engineering has introduced approximately...
Article
As the transistor count and performance expectations of integrated circuits have grown, their power consumption has approximately doubled every thirty-six months. To minimize power consumption and maintain dielectric reliability, the supply voltage of microprocessors has been scaled down. As the operating voltage decreases, more current is required...

Network

Cited By

Projects

Project (1)