Mageda Sharafeddin

Mageda Sharafeddin
Lebanese University · Faculty of Science

Doctor of Engineering

About

17
Publications
6,479
Reads
How we measure 'reads'
A 'read' is counted each time someone views a publication summary (such as the title, abstract, and list of authors), clicks on a figure, or views or downloads the full-text. Learn more
94
Citations
Additional affiliations
October 2015 - present
Lebanese University
Position
  • Lecturer
September 2015 - present
Lebanese American University
Position
  • Lecturer
October 2014 - January 2015
American University of Beirut
Position
  • Lecturer
Description
  • Computer Architecture

Publications

Publications (17)
Article
In this work, we propose a high performance distributed system that consists of several middleware servers each connected to a number of FPGAs with extended solid state storage that we call reconfigurable active solid state device (RASSD) nodes. A full data communication solution between middleware and RASSD nodes is presented. We use seismic data...
Article
While cloud computing has provided major benefits by maximizing the use of resources within a cloud, the current solutions still face many challenges. In this paper, we propose performance enhancements for cloud computations, provided by integrating hardware acceleration into the computation services. We extend the Hadoop framework by adding provis...
Article
We propose a high performance distributed system that consists of several middleware servers (MWS) each connected to a number of FPGAs with extended solid state storage that we call reconfigurable active solid state device (RASSD) nodes. A MWS manages a group of RASSD nodes and bridges the connection between a client and the RASSD nodes within a co...
Article
Full-text available
Programming FPGAs requires advanced hardware design skills which limits their adoption in data centres. FPGA vendors have provided high level synthesis (HLS) tools to build register transfer level (RTL) specifications from designs provided in high level languages. We present a suite of C and C++-based hardware accelerators for the Purdue MapReduce...
Preprint
Full-text available
We propose a high performance distributed system that consists of several middleware servers (MWS) each connected to a number of FPGAs with extended solid state storage that we call reconfigurable active solid state device (RASSD) nodes. A MWS manages a group of RASSD nodes and bridges the connection between a client and the RASSD nodes within a co...
Conference Paper
Full-text available
The main contribution of this paper is providing an architecture for mobile users to authenticate user identity through short text phrases using robust open source voice recognition library ALIZE and speaker recognition tool LIA_RAL. Our architecture consists of a server connected to a group of subscribed mobile devices. The server is mainly needed...
Article
Full-text available
This article describes and evaluates a small, out-of-order, simultaneous multithreaded (SMT) core architecture suitable for power constrained microprocessors, such as manycore microprocessors for high performance computing. The architecture does not require a reorder buffer (ROB) or physical registers for register renaming and instruction retiremen...
Conference Paper
Full-text available
Modern high level synthesis (HLS) tools generate Register Transfer Language (RTL) from designs specified in high level languages such as C. By raising the design abstraction level while still promising competitive performance, HLS tools can greatly reduce design effort and time. Contemporary HLS tools can support most manual hardware design optimiz...
Article
Full-text available
In this article, we propose new extensions to Hadoop to enable clusters of reconfigurable active solid-state drives (RASSDs) to process streaming data from SSDs using FPGAs. We also develop an analytical model to estimate the performance of RASSD clusters running under Hadoop. Using the Hadoop RASSD platform and network simulators, we validate our...
Conference Paper
This paper presents a novel high performance substrate for building energy-efficient out-of-order superscalar cores. The architecture does not require a reorder buffer or physical registers for register renaming and instruction retirement. Instead, it uses a large number of virtual register IDs for register renaming, a physical register file of the...
Conference Paper
High-performance superscalar architectures used to exploit instruction level parallelism in single-thread applications have become too complex and power hungry for the multicore processors era. We propose a new architecture that uses multiple small latency-tolerant out-of-order cores to improve single-thread performance. Improving single-thread per...
Conference Paper
Full-text available
We have recently proposed a Distributed Reconfigurable Active SSD computation platform (RASSD) for processing data-intensive applications at the storage node itself, without having to move data over slow networks. In this paper, we present the design of an operating system (OS) for the RASSD node. RASSD OS is a multitasking real-time operating syst...
Conference Paper
Full-text available
Since the introduction of the first industrial out-of-order superscalar processors in the 1990s, instruction buffers and cache sizes have kept increasing with every new generation of out-of-order cores. The motivation behind this continuous evolution has been performance of single-thread applications. Performance gains from larger instruction buffe...
Conference Paper
Full-text available
paper, we propose to combine active solid state drives and reconfigurable FPGAs into a storage-compute node to use as a building block in a distributed, high performance computation platform for data intensive applications. We propose a complete framework for middleware functionality through an API abstraction layer that hides the complexity of acc...
Conference Paper
Full-text available
This paper describes a novel 2-wide in-order simultaneous multithreading core architecture that performs fine-grain data-dependence based threaded execution in hardware, when there is only one available software thread. Performance simulation on a subset of Spec 2000 benchmarks shows our architecture gives 7% average reduction in single-thread exec...
Article
Full-text available
Previous models of software development projects have failed to represent people productivity accurately. In this paper, we present a model characterized by realistic productivity curves and flexibility in choosing resource factors in a software engineering project. A two-mode mathematical model similar to PutnamNorden model js presented. The propo...

Network

Cited By