Loïc Lagadec

Loïc Lagadec
ENSTA Bretagne · Lab-STICC

Professor

About

120
Publications
8,120
Reads
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470
Citations
Additional affiliations
September 2012 - present
ENSTA Bretagne
Position
  • Professor (Full)
February 2001 - August 2012
Université de Bretagne Occidentale
Position
  • Professor (Assistant)

Publications

Publications (120)
Chapter
A Sensor Network (S.N.) is responsible for performing two main activities: (1) observation/measurement, which means accumulating data collected at each sensor node; (2) transferring the collected data to processing centers (e.g., Smart Sensors, Smart Fusion Servers) within the S.N. The infrastructure of Marine/Deep-sea Observatory is an Underwater...
Conference Paper
Leader Election is a classical problem in distributed systems in which one of the processes is chosen to organize a common task. In wireless sensor networks a leader is often a node of minimum or maximum value such as its identifier, remaining battery life, level of trust or its x- or y-coordinate in the plane which allows to start an algorithm to...
Conference Paper
The ever-growing cost of both training and inference for state-of-the-art neural networks has brought literature to look upon ways to cut off resources used with a minimal impact on accuracy. Using lower precision comes at the cost of negligible loss in accuracy. While training neural networks may require a powerful setup, deploying a network must...
Preprint
The ever-growing cost of both training and inference for state-of-the-art neural networks has brought literature to look upon ways to cut off resources used with a minimal impact on accuracy. Using lower precision comes at the cost of negligible loss in accuracy. While training neural networks may require a powerful setup, deploying a network must...
Article
Full-text available
Homomorphic Encryption (HE) aims to perform computations on encrypted data. Still in research stage, a lot of HE schemes have been created but their comparison remains costly as execution exhibits prohibitive costs. PAnTHErS is a HE schemes modeler. Modeling with a common formalism allows the evaluation of input parameters variation impact on perfo...
Article
Full-text available
In wireless sensor and IoT networks dedicated to smart-cities, a leader node performs critical tasks such as generating encryption/decryption keys. In this paper, the leader is the node situated at the extreme left of the network. It is the node which starts the algorithm of searching the boundary nodes. These nodes will be used to monitor any sens...
Conference Paper
Full-text available
One of the interesting techniques for leader election is used in the WBS (Wait Before Starting) algorithm, in which each node in the network will wait for a time corresponding to its value before starting to send the first message to neighbours. This means that the node with the smallest value becomes the leader and it also starts first. This appro...
Conference Paper
Full-text available
The main parameter studied in a simulation of a Wireless Sensor Network is the lifetime of the network. In other words, the state of the battery of each node. That is why modelling correctly the battery is very important to obtain realistic results. In real applications, many types of batteries can be considered, where their lifetime depends on the...
Chapter
A leader node in Ad hoc networks and especially in WSNs and IoT networks is needed in many cases, for example to generate keys for encryption/decryption, to find a node with minimum energy or situated in an extreme part of the network. In our work, we need as a leader the node situated on the extreme left of the network to start the process of find...
Conference Paper
When we deal with the deployment structure of Wireless Sensor Networks (WSNs) used in applications where the zone-of-interest is not accessible by humans, like fire forest detection, military applications, etc., random deployment is often the main or even the only practical solution that can be chosen. One of the main issues in this deployment is t...
Conference Paper
Full-text available
A random deployment of Wireless Sensor Networks (WSNs) is often the basic structure used in the context of fire forest detection, military applications or any situation where the zone-of-interest is not accessible by humans. The main problematic in this kind of deployment is the formation of gaps or voids, which represent a zone which is not covere...
Conference Paper
A leader node in Ad hoc networks and especially in WSNs and IoT networks is needed in many cases, for example to generate keys for encryption/decryption, to find a node with minimum energy or situated in an extreme part of the network. In our work, we need as a leader the node situated on the extreme left of the network to start the process of find...
Article
This paper proposes a novel approach for the hardware virtualization of FPGA resources, based on overlay architectures. Overlays are reconfigurable architectures synthesized on top of commercial-of-the-shelf (COTS) FPGAs. They have demonstrated to improve portability, speed up reconfiguration, and promote resource abstraction hence durability. This...
Conference Paper
Reconfigurable computing is rapidly establishing itself as a major discipline, involving the use of reconfigurable devices for computing purposes. This paper proposes the ORRes approach for a time-sharing of reconfigurable resources. We investigate the overlay architecture at the hardware layer to ensure the bitstream compatibility between heteroge...
Conference Paper
Full-text available
Reconfigurable cores support post-release updates which shortens time-to-market while extending circuits’ lifespan. Reconfigurable cores can be provided as hard cores (ASIC) or soft cores (RTL). Soft reconfigurable cores outperform hard reconfigurable cores by preserving the ASIC synthesis flow, at the cost of lowering scalability but also exacerba...
Conference Paper
Full-text available
Sensor networks are now one of the key technologies for the Internet of Things (IoT). An IP-based sensor network allows a natural participation of sensor nodes to the IoT. Smart IoT systems are always constrained by real-time processing. Edge computing can be used to address this constraint. In such system, sensor nodes are often in need of more pr...
Presentation
Full-text available
Présentation des travaux de Theotime Bollengier, sur les overlays grain-fin.
Conference Paper
Overlays are reconfigurable architectures synthesized on commercial of the shelf (COTS) FPGAs. Overlays bring some advantages such as portability, resources abstraction, fast configuration, and can exhibit features independent from the host FPGA. We designed a fine-grained overlay implementing novel features easing the management of such architectu...
Article
Security and safety are more and more impor-tant in embedded system design. A key issue, hence lies in the ability of systems to respond safely when errors occur at runtime, to prevent unacceptable behaviors that can lead to failures or sensitive data leakage. In this paper, we propose a design approach that automatically generates on-chip mon-itor...
Poster
Full-text available
The incorporation of traditional FPGAs in datacenters is a solution brought for delivering a powerful, flexible and energy-efficient cloud computing. In this context, we propose a software/hardware framework for integrating virtualized FPGA-based hardware accelerators into traditional cloud computing systems. The virtual FPGAs are FPGA-like overlay...
Conference Paper
Full-text available
Les overlays connaissent actuellement un regain d’intérêt car ces architectures offrent plusieurs avantages : disponibilité (une overlay est une IP), facilité de programmation, rapidité de configuration. Cet article présente une plateforme pour l’exploitation d’overlays comme accélérateurs matériels dans un cadre cloud. L’accent est mis sur la migr...
Article
Full-text available
High level synthesis (HLS) refers to an automated process that creates a digital hardware from an algorithmic description of some computation. From the perspective of Smalltalk, this process consists of converting code from the oriented object level to the register transfer level (RTL), that supports direct compilation to the hardware level. In thi...
Conference Paper
Full-text available
Les FPGAs virtuels présentent de nombreux avantages : portabilité du bitstream, gestion de l'obsolescence, etc. acquis au prix d'une perte en performances (surface, fréquence) et de la mise au point d'un environnement d'exploitation adéquat. Cet article présente Phadeo, un environnement issu de Madeo, développé dans le cadre du projet ANR ARDyT, qu...
Conference Paper
Full-text available
Virtual prototyping supports fast exploration of design space for new embedded platforms. Uses of FPGA in critic environment requires to design adapted circuits at the cheapest cost possible. We then aim at developing a low-cost fault-tolerant FPGA. This work relies on a modular design flow and embedding custom logic units ranging from medium-to-co...
Conference Paper
Nowadays, new systems are by nature distributed and built around existing systems. The concept of System of systems (SoS) has become the key for creating new systems. Modeling is a central issue of SoS design and evolution. Since subsystems of a SoS can be modeled in different languages, the SoS modeling environment should be able to handle indisti...
Article
This article describes TBES, a software end-to-end environment for synthesizing multitask applications on FPGAs. The implementation follows a template-based approach for creating heterogeneous multiprocessor architectures. Heterogeneity stems from the use of general-purpose processors along with custom accelerators. Experimental results demonstrate...
Article
Improvements in system cost, size, performance, power dissipation, and design turnaround time are the key benefits offered by System-on-Chip designs. However they come at the cost of an increased complexity and long development cycles. Integrating reconfigurable cores offers a way to increase their flexibility and lifespan. However the integration...
Conference Paper
Application developers request safe and reliable layers on which to operate. Reliability has been assumed for years, as CMOS circuits were correct-by-construction. Nowadays, shrinking transistor size implies a reduction in yield and reliability of SoC, due to the presence or appearance of physical defects in the circuit. Nanotechnologies face same...
Article
Full-text available
The tremendous progress of the IC industry during the last decades enables the creation of complex System-on-Chip (SoC) solutions addressing more and more challenging requirements. However, as the CMOS technology approaches its physical limits, the constraints on SoC increase, demanding for different design styles such as asynchronous and power-awa...
Conference Paper
Evolution of Systems-On-Chip (SoC) increases the challenge of verification and post-silicon debug. Nowadays, Assertion Based Verification (ABV) is a widely used methodology. Languages like PSL (Property Specification Language) or SVA (System Verilog Assertions) allows engineers to define properties at Register Transfer Level (RTL). Properties can t...
Conference Paper
Embedded systems often implement safety critical applications making security a more and more important aspect in their design. Control-Flow Integrity (CFI) attacks are used to modify program behavior and can lead to learn valuable information directly or indirectly by perturbing a system and creating failures. Although CFI attacks are well-known i...
Conference Paper
Full-text available
Virtualization has been a key enabler for trading raw performances for programmability, straightforward reuse and higher abstraction in the software world. Similarly, Virtual FPGAs define intermediate fabrics, on which to implement applications regardless of the physical target. In order to make legacy applications run on up-to-date targets, only p...
Conference Paper
Full-text available
Cet article de synthèse introduit la notion de virtualisation, appliquée aux architectures recon-figurables et en recense des cas d'usage significatifs. Ces usages balaient des préoccupations aussi diverses que la durabilité des produits (gestion de l'historique) ou le support à l'expéri-mentation de nouveau dispositifs (promotion de l'innovation m...
Article
The current integrated circuit technologies are approaching their physical limits in terms of scaling and power consumption, in this context, the electronic design automation (EDA) industry is pushed towards solving ever more challenging problems in terms of performance, scalability and adaptability. Meeting these constraints needs innovation at bo...
Book
Smalltalk is an exciting object-oriented language in which even primitive values are uniformly handled as normal objects described by classes that one can browse and extend. Smalltalk was born during the seventies, but the ideas behind currently available implementations are still modern and innovative. Smalltalk benefits from being a highly expres...
Conference Paper
In the context of embedded systems design, the growing heterogeneity of systems leads to increasingly complex and unreliable tool chains. The Model-Driven Engineering (MDE) community has been making considerable efforts to abstract tool languages in meta-models, and to offer model transformation mechanisms for model exchanges. However, the interope...
Conference Paper
Our contribution lies in offering a fast and parametrized domain-space exploration to the designer, whose expertise drives the whole process while staying the actor of added-value creation. In this paper, we present two new features and two important improvements of our H-MPSoC synthesis framework. The first one is a new template-based approach for...
Book
Numéro spécial du Symposium en Architecture de Machines SympA'14
Conference Paper
Over the last decade many academic and industrial system synthesis and codesign tools have been proposed to designers. However most of these tools are based on IP Libraries but either these libraries are incomplete or are simply not adapted to the targets and constraints. It means that something important is missing when it comes to real implementa...
Conference Paper
Full-text available
Nowadays, the use of mobile applications and terminals faces fundamental challenges related to energy constraint. This is due to the limited battery lifetime as compared to the increasing hardware evolution. Video streaming is one of the most energy consuming applications in a mobile system because of its intensive use of bandwidth, memory and proc...
Conference Paper
In this paper we propose an ESL synthesis framework which, from the C code of an application and a description of a generic architecture, automatically explores and generates a complete synthesizable version of a H-MPSoC architecture along with the adapted code application. We developed a Design Space Exploration (DSE) algorithm that merges hardwar...
Article
Full-text available
In pre-commitment of 74 du Grenelle de la mer "develop a methodology and a national strategy for shoreline management, the strategic retreat and defense against the sea [...]," a synthesis of work on observatories of shoreline in mainland France and overseas departments was carried out by BRGM at the request of MEEDDM. The findings of this study em...
Article
Full-text available
The ever-growing needs of functions in embedded systems along with integration capacities lead to the develop-ment of Multi-Processor Systems-on-Chip (MPSoC). But the complexity gap of the architecture design once again raises the problem of the productivity and the lack of System Synthesis tools. In this paper, we propose a new kind of system-leve...
Book
http://www.esug.org/wiki/pier/Conferences/2012/International-Workshop---IWST-2012/scp_cfp
Article
The integrated circuit industry continues to progress rapidly deepening the gap in between the technological breakthroughs and the electronic design automation industry. This gap is even more problematic in the context of physical design, the last automation level between applications and the technology. The challenges of meeting the physical and p...
Article
Full-text available
Résumé Les machines virtuelles mettent à disposition des développeurs un paradigme de programmation haut niveau couplé à un ensemble de services. Cela se traduit par la réduction des temps de développement et la production d'applications portables. Aujourd'hui des composants comme les systèmes sur puce (SoCs) embarquent un nombre élevé de ressource...
Conference Paper
As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design spac...
Conference Paper
The physical design automation is a difficult problem due to the huge number of devices, and physical constraints to be met. The Model-Driven Engineering (MDE) approach aims to tackle the complexity of software development using a high level method based on models and transformations. While this approach is used for High-Level circuit synthesis the...
Conference Paper
In order to cope with the increasing complexity of embedded applications as well as their fast evolution, flexible systems with high-performance are mandatory. In this context, reconfigurable system-on-chip solutions that meet application needs have become common. However, the innovation race shrinks time-to-market and puts high pressure on designe...
Article
Full-text available
As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of dif-ferent fabrics and architectures are currently under investigation. This work presents a NASIC-compliant application-specific computing architecture template along with its...
Conference Paper
Full-text available
As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design spac...