Kothuru Bharath

Kothuru Bharath
Indraprastha Institute of Information Technology | IIITD · ece

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2
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5
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Citations since 2017
1 Research Item
5 Citations
20172018201920202021202220230.00.51.01.52.0
20172018201920202021202220230.00.51.01.52.0
20172018201920202021202220230.00.51.01.52.0
20172018201920202021202220230.00.51.01.52.0
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Introduction
Skills and Expertise
Electronics and Communication Engineering

Publications

Publications (2)
Fig. 1: An 8T 1R-1W Dual-Port SRAM cell
Fig. 2: The basic block diagram of an asynchronous FIFO 
Fig. 3: FIFO timing diagram for the scenario in which f wclkf ≤ f rclkf 
Fig. 4: Block diagram for the design with f wclkm ≤ f rclkm
+1 Fig. 5: Timing diagram for f wclkm ≤ f rclkm with T = T rclkm
Asynchronous 1R-1W dual-port SRAM by using single-port SRAM in 28nm UTBB-FDSOI technology
Conference Paper
Full-text available
  • Sep 2017
With the advancement in technology nodes, the number of components operating in different clock domains in a System on Chip (SoC) increases. Asynchronous multi-port memory with dedicated write and read ports is used to allow data to cross clock domain boundaries. The dual-port memory architecture introduced in this paper, is based on the Single-Por...
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