Ken Takeuchi

The University of Tokyo | Todai · Department of Electrical Engineering and Information Systems

This article proposes a privacy-aware data-lifetime control NAND flash system (PDLCS) that changes the data-lifetime flexibly for privacy protection. The proposed PDLCS consists of four proposed techniques: 1) inverse Huffman-coding V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> modulation...

This Special Issue of the IEEE Journal of Solidstate Circuits highlights some of the best papers presented at the 33rd Symposium on VLSI Circuits, held on June 10–14, 2019, at Rihga Royal Hotel Kyoto, Kyoto, Japan. Industry and university engineers from all over the world reported innovative new techniques and state-of-the-art results. Articles pre...

This paper analyzes the system-level performance of Storage Class Memory (SCM)/NAND flash hybrid solid-state drives (SSDs) and SCM/NAND flash/NAND flash tri-hybrid SSDs in difference types of NAND flash memory. There are several types of NAND flash memory, i.e. 2-dimensional (2D) or 3-dimensional (3D), charge-trap type (CT) and floating-gate type (...

This paper analyzes the optimal SSD configuration including emerging non-volatile memories such as quadruple-level cell (QLC) NAND flash memory [1] and storage class memories (SCMs). First, SSD performance and SSD endurance lifetime of hybrid SSD are evaluated in four configurations: 1) single-level cell (SLC)/QLC NAND flash, 2) SCM/QLC NAND flash,...

This paper presents the Step-by-Step Design of memory hierarchy for heterogeneously-integrated SCM/NAND flash storage. The heterogeneously-integrated storages utilize multiple types of non-volatile memories such as storage class memories (SCMs) and NAND flash memories. SCMs are further classified to memory-type and storage-type. NAND flash memories...

Using storage class memories (SCMs) as nonvolatile cache of NAND flash memory is a promising solution for the high-performance storage. However, the problem is the high SCM cost per bit which is about ten times higher than NAND flash and the optimal SCM capacity is application dependent. The optimum SCM capacity is conventionally determined manuall...

This Special Issue of the IEEE Journal of Solid-State Circuits highlights some of the best papers presented at the 32nd Symposium on VLSI Circuits, held on June 18–22, 2018, at the Hilton Hawaiian Village, Honolulu, HI, USA. Industry and university engineers from all over the world reported innovative new techniques and state-of-the-art results. Pa...

This paper proposes Value-Aware solid-state drive (SSD) with fast access speed and low power consumption by eliminating error-correcting code (ECC). Value-Aware SSD utilizes the error tolerance of image recognition application using a deep neural network (DNN) to enhance reliability. In a previous paper, which proposes Value-Aware SSD, fast ECC dec...

Adaptive artificial neural network (ANN)-coupled low-density parity-check (LDPC) error-correcting code (ECC) (ANN-LDPC ECC) is proposed to increase acceptable errors for various nand flash memories. The proposed ANN-LDPC ECC can be the universal solutions for 3-D and 2-D, charge-trap and floating-gate nand flash memories. In 3-D nand flash, lateral...

Heterogeneously-integrated memory system is configured with various types of storage class memories (SCMs) and NAND flash memories. SCMs are faster than NAND flash, and they are divided into memory and storage types with their characteristics. NAND flash memories are also classified by the number of stored bits per memory cell. These non-volatile m...

Advancement of process technologies has significantly improved the performance of semiconductor devices and consequently of circuits. Device lifetime, on the other hand, has been unavoidably compromised through the introductions of new materials, new process technologies, etc. Mitigating measures against transient degradation of circuit performance...

This chapter discusses how to build dependable nonvolatile memory systems that range from the SD card to high-performance enterprise storage. The nonvolatile memory systems are mainly composed of NAND flash memories because of their high bit density. However, the reliability of the NAND flash memory is degrading along with the memory-cell scaling....

As a comprehensive solution based on the data access frequency, this paper proposes word-line batch V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> modulation (WBVM) to improve the reliability of 2-D and 3-D-triple-level-cell (TLC) nand flash memories. Proposed WBVM modulates the threshold v...

In this paper, versatile triple-level cell (TLC) NAND flash memory control with four proposed techniques, Read-Hot/Cold Migration, Read Voltage Control (RVC), Edge Word-Line Protection (EWLP), and Worst Page Detection (WPD), is proposed for data center application solid-state drives (SSDs). To apply the optimal reliability enhancement techniques fo...

A hybrid of storage class memory (SCM) and NAND flash is a promising technology for high performance storage. Error correction is inevitable on SCM and NAND flash because their bit error rate (BER) increases with write/erase (W/E) cycles, data retention, and program/read disturb. In addition, scaling and multi-level cell technologies increase BER....

In order to improve performance of solid-state drives (SSDs), hybrid SSDs have been proposed. Hybrid SSDs consist of more than two types of NAND flash memories or NAND flash memories and storage-class memories (SCMs). However, the cost of hybrid SSDs adopting SCMs is more expensive than that of NAND flash only SSDs because of the high bit cost of S...

In order to reduce the memory cell errors in real-usage of NAND flash-based SSD, real usage-based precise reliability test for NAND flash of SSDs has been proposed. Reliability of the NAND flash memories of the SSDs is seriously degraded as the scaling of memory cells. However, conventional simple reliability tests of read-disturb and data-retentio...

NAND flash memory-based solid-state drives (SSDs) are increasingly being used in both consumer and enterprise storage markets, due to their superior performance over hard disk drives (HDDs) and continuous bit cost reductions. With multiple-level cell technology memory device is capable of trading off the performance and endurance with bit density....

This study analyzes the influence of the interval of time (t S-P) between write/erase endurance stress and programming the final data for the data-retention and read-disturb error evaluations in 1X nm triple-level cell (TLC) NAND flash memories. During the interval of time after the write/erase endurance stresses, electrons are de-trapped from the...

This paper analyzes the best mix of memories in a tri-hybrid solid-state drive (SSD) with storage class memory (SCM) and multi-level cell (MLC)/triple-level cell (TLC) NAND flash memory. SCM is fast but its cost is high. Although MLC NAND flash memory is slow, it is more cost effective than SCM. For further cost efficiency, TLC NAND flash memory is...

In order to realize solid-state drives (SSDs) with high performance, low energy consumption and high reliability, storage class memory (SCM)/multi-level cell (MLC) NAND flash hybrid SSD has been proposed. Algorithm of the hybrid SSD should be designed according to SCM specifications and workload characteristics. In this paper, SCMs are used as non-...

A novel method adaptively controls the comparator bias current in a boost converter for sensor-data storage on Resistive Random Access Memory (ReRAM). ReRAM is ideal for low-power sensors because it is faster and lower voltage than NAND flash. However, ReRAM's voltage design needs to consider program current variation due to data pattern dependency...

NAND flash memory's reliability degrades with increasing endurance, retention-time and/or temperature. After a comprehensive evaluation of 1X nm triple-level cell (TLC) NAND flash, two highly reliable techniques are proposed. The first proposal, quick low-density parity check (Quick-LDPC), requires only one cell read in order to accurately estimate...

Solid-state drives (SSDs), composed of NAND flash memories, are replacing hard disk drives (HDDs) rapidly. In addition, storage class memories (SCMs) bridge the bandwidth gap between DRAM and NAND flash, thus introducing SCM to SSD further improves the solid storage performance. Different from schemes that use SCM to store file system metadata or l...

A solid-state drive (SSD) with 1Xnm triple-level cell (TLC) NAND flash is proposed for low cost data storage applications with long-term data-retention requirements. Specifically, cold data storage requires 20 years data-retention with 100 write/erase (W/E) cycles, whereas digital archive storage requires 1000 years retention time with 1 W/E cycle....

A novel error correction scheme, called reset-check-reverse-flag (RCRF), is proposed to improve the reliability of storage class memories (SCMs). RCRF divides the conventional Bose-Chaudhuri-Hocquenghem (BCH) code length into multiple subsections. One flag bit is added to each subsection to correct program errors. By reversing the flag bit and user...

In order to realize the high-performance solid-state drives (SSDs), SCM/NAND flash hybrid SSD has been proposed, which add Storage Class Memory (SCM) as a non-volatile cache to the NAND flash based SSD. This paper provides cache operation guidelines and the optimal SCM specifications for the hybrid SSD. Two algorithms, the hybrid SSD with 1) read-w...

The future storage class memory (SCM) can be comparable with NAND flash in terms of cost, and with DRAM from the perspective of speed. There are 3 primary memory technology candidates that match the target requirements for SCM: ReRAM, PCM, and MRAM. The future SCM-based solid state drive (SSD) shows advantages of high performance and low power cons...

Carbon Nanotube (CNT) memory has a simple structure, low voltage, low current, and fast switching mechanism, and endurance up to 10 12 cycles has been demonstrated [1]. In order to optimize set and reset algorithms and understand the mechanisms of CNT reliability, this work studies the CNT after 10 7 endurance cycles for different combinations of s...

This chapter introduces the design of three-dimensional (3D) NAND flash memory with the implications from the system side. For conventional two-dimensional (2D) scaling, it is facing various limitations such as lithography cost and cell-to-cell coupling interference. To sustain the trend of bit-cost reduction beyond 10 nm technology node, 3D NAND f...

In emerging non-volatile memories, nano-random access memory (NRAM) has advantages of small program current and high endurance compared with resistive RAM (ReRAM) and phase-change RAM (PRAM). This work comprehensively investigates NRAM set and reset program characteristics by measuring a 116 nm 4 Mbit NRAM cell array. Specifically, reset is found m...