Jos Huisken

Eindhoven University of Technology | TUE · Electronic Systems

For sub-10nm technology generations, the conventional scaling strategy, viz. simply decreasing poly pitch (PP) and metal pitch (MP) , does no longer bring sufficient area reduction to maintain Moore’s Law [1]. To continue the scaling rat race, standard-cell library designers are now implementing innovative library-cell concepts (referred to as...

We present a systematic evaluation and optimization of a complex bio-medical signal processing application on the BrainWave prototype system, targeted towards ambulatory EEG monitoring within a tiny power budget of $< $ 1 mW. The considered BrainWave processor is completely programmable, while maintaining energy-efficiency by means of a Coarse-Gr...

Integrated circuits operating in the near/subthreshold region offer low energy consumption. However, due to the constrained voltage scalability of SRAMs, efficient power delivery is difficult to achieve. A traditional implementation would require at least two distinct voltage supplies generated by possibly two power converters. In this article, a n...

Cell-aware test (CAT) explicitly targets faults caused by defects inside library cells to improve test quality, compared with conventional automatic test pattern generation (ATPG) approaches, which target faults only at the boundaries of library cells. The CAT methodology consists of two stages. Stage 1, based on dedicated analog simulation, librar...

Temporal Convolutional Networks (TCNs) involving mono channels as input, have shown superior performance compared to state-of-the-art sequence detection recursive networks in a variety of applications. TCNs leverage the concept of dilated causal convolution for a wider receptive field coverage of input (mono) channels, which requires scaling the de...

A memory device having complementary global and local bit-lines, the complementary local bit-lines being connectable to the complementary global bit-lines by means of a local write receiver which is configured for creating a full voltage swing on the complementary local bit lines from a reduced voltage swing on the complementary global bit lines. T...

This article gives an overview of a methodology for building dynamical electronic systems. As an example a part of a system for epileptic seizure prediction is used, which monitors EEG signals and continuously calculates the largest short-term Lyapunov exponents. In dynamical electronic systems, the cost of exploitation, for instance energy consump...

An ultra low power sense amplifier circuit for amplifying a low swing input signal to a full swing output signal is disclosed. In one aspect, the amplifier circuit includes a first amplifier stage for pre-amplifying the input signal to an intermediate signal on its internal nodes, a second amplifier stage for amplifying the intermediate signal to t...

Wireless Sensor Nodes (WSN) have a wide range of applications in health care and life style monitoring. Their severe energy constraint is often addressed through minimizing the amount of transmitted data by way of energy-efficient on-node signal processing. The rationale for this approach is that a large portion of WSN energy is consumed by the rad...

Instruction memory organisations have been pointed out as one of the major sources of energy consumption in embedded systems. As embedded systems are characterised by restrictive resources and a low-energy budget, any enhancement that is introduced into this component of the system will allow embedded designers not only to decrease the total energy...

System scenario methodologies propose the use of different scenarios, e.g., different platform configurations, in order to exploit variations in computational and memory needs during the lifetime of an application. In this paper several extensions are proposed for a system scenario based methodology with a focus on improving memory organisation. Th...

Medical diagnosis and healthcare are at the onset of a revolution fueled by improvements in smart sensors and body area networks. Those sensor nodes' computation and memory requirements are growing, but their energy resources do not increase; thus, more energy-efficient memories and processors are required. New circuit-design techniques that drasti...

Process variability severely impacts the performance of circuits operating in the subthreshold domain. Among other reasons, this mainly stems from the fact that subthreshold current follows a widely spread Log-Normal distribution. In this paper we introduce a new transistor sizing methodology for standard cells. Our premise relies on balancing the...

This paper presents litho friendly circuit techniques for variability resilient low power 8T SRAM. The new local assist circuitry achieves a state-of-the-art low energy and variability resilient WRITE operation and improves the degraded access speed of SRAM cells at low voltages. Differential VSS bias increases the variability resilience. The physi...

Data-parallel processing is a widely applicable technique, which can be implemented on different processor styles, with varying capabilities. Here we address single or multi-core data-parallel instruction-set processors. Often, handling and reorganisation of the parallel data may be needed because of diverse needs during the execution of the applic...

This paper presents a voltage-scalable digital signal processing system designed for the use in a wireless sensor node (WSN) for ambulatory monitoring of biomedical signals. To fulfill the requirements of ambulatory monitoring, power consumption, which directly translates to the WSN battery lifetime and size, must be kept as low as possible. The pr...

This paper describes an ultra-low power (ULP) single chip transceiver for wireless body area network (WBAN) applications. It supports on-off keying (OOK) modulation, and it operates in the 2.36–2.4 GHz medical BAN and 2.4–2.485 GHz ISM bands. It is implemented in 90 nm CMOS technology. The direct modulated transmitter transmits OOK signal with 0 dB...

An ultra low energy, 128 kbit 6T SRAM in 90 nm LP CMOS with energy consumption of 4.4 pJ/access, operating at 80 MHz for the wireless sensor applications is developed. The variability resilient and low power techniques developed include innovation in the local architecture with the use of local read/write assist circuitry. The energy-efficient hier...

In order to provide better services to elderly people, home healthcare monitoring systems have been increasingly deployed. Typically, these systems are based on wireless sensor nodes, and should utilize very low energy during their lifetimes, as they are powered by scavengers. In this article, we present an ultra-low power processing system for a w...

Instruction memory organization is pointed out as one of the major sources of energy consumption in embedded systems. As embedded systems are characterized by restrictive resources and low energy budget, any enhancement in this component allows not only to decrease the total energy consumption, but also to have a better distribution of the energy b...

This design sets a record low energy consumption (average RD/WR) of 2.65pJ/access for a 64kbit embedded SRAM operating at 90MHz in 65nm LP CMOS. This low energy and variability resilient SRAM macro ensures write-ability with an innovative Mimicked Negative Bit-line technique. The novel low energy Charge Limited Sequential sense amplifier consumes 1...

This paper describes a mixed-signal ECG System-on-chip (SoC) that is capable of implementing configurable functionality with low-power consumption for portable ECG monitoring applications. A low-voltage and high performance analog front-end extracts 3-channel ECG signals and single channel impedance measurement with high signal quality. A custom di...

Sub-threshold operation has been proven to be very effective to reduce the power consumption of circuits when high performance is not required. Future low power systems on chip are likely to consist of many sub-systems operating at different frequencies and VDDs from super-threshold to sub-threshold region. Synchronizers are therefore needed to int...

In order to minimize power consumption without sacrificing much latency performance, wake-up radios are employed to assist the main radio for low power channel monitoring. This paper presents the design and implementation of an ultra-low power digital baseband (DBB) circuit for a wake-up radio. In a 90nm CMOS process, the circuit running at a 800kH...

This paper presents a system design study for wearable sensor devices intended for healthcare and lifestyle applications based on ECG, EEG and activity monitoring. In order to meet the low-power requirement of these applications, a dual-core signal processing system is proposed which combines an ultra-low-power bio-medical Application Specific Inst...

Due to the unattended nature of WSN (Wireless Sensor Network) deployment, each sensor can be subject to physical capture, cloning and unauthorized device alteration. In this paper, we use the embedded SRAM, often available on a wireless sensor node, for secure data (cryptographic keys, IDs) generation which is more resistant to physical attacks. We...

In this paper, the authors present an event-driven system with resources to run applications with different degrees of complexity in an energy-aware way. The architecture uses effective system partitioning to enable duty cycling, SIMD instructions, power gating, voltage scaling, multiclock domains, multivoltage domains, and extensive clock gating....

In order for wireless body area networks to meet widespread adoption, a number of security implications must be explored to promote and maintain fundamental medical ethical principles and social expectations. As a result, integration of security functionality to sensor nodes is required. Integrating security functionality to a wireless sensor node...

Wireless body-area networks (WBAN) are used for communication among sensor nodes operating on, in or around the human body, e.g. for healthcare purposes. In view of energy autonomy, the total energy consumption of the sensor nodes should be minimized. Because of their low complexity, a combination of the super-regenerative (SR) principle [1-3] and...

This paper presents a novel low-to-high level shifter that enables having voltage domains with substantially different supply voltages from near-threshold to full supply voltage. The level shifter was designed in a 90 nm CMOS technology and uses thick-oxide transistors, non-minimum channel length transistors, along with novel circuit structures to...

We present the design of 4 Application Specific Instruction Set Processors (8-bit, 32-bit, 64-bit and 128-bit ASIP) which provide typical 16-bit general instructions and accelerate a common cryptographic domain. The ASIPs support the following security services: data confidentiality, data authentication, data integrity and replay attack protection...

Sub-threshold operation has been proved to be successful to achieve minimum energy consumption. It is well known that the sub-threshold device sizing is different from super-threshold due to different current behavior. The previously reported sub-threshold sizing methods assume that the current is proportional to the transistor width. However, we h...

An Ultra Low Power (ULP) biomedical System-on Chip (SoC) has been developed for efficient ECG/EEG signal processing in a Body Area Network environment. This experimental SoC explores the use of event-driven peripheral modules that autonomously interact with external sensors together with the use of an Application-Specific-Instruction-set Processor...

Leakage power (active and standby) is becoming increasingly dominant part of total power consumption in nano-scaled CMOS circuits. Present day commercial libraries provide multiple vt class cells to optimize active leakage power and circuit timing in functional/active mode, while techniques such as power gating have specifically addressed standby l...

In this paper we present a methodology that enables mapping and scheduling of a dynamic real-time medical signal processing application onto an MPSoC platform. We apply the Task Concurrency Management (TCM) methodology on Lyapunov Exponent calculator, which is a part of an epileptic seizure predictor. TCM requires a division of an application into...

This paper presents a low power ultra-wide band digital receiver baseband architecture for handling IEEE 802.15.4a packets in real-time. Real-time processing allows duty cycling of the analog frontend, which is key to achieve low power consumption. The architecture consists of a programmable application specific instruction set processor and a set...

A Variability resilient 128kbit 6T SRAM with energy consumption of 4.4pJ/access, operating at 80MHz for wireless sensor applications is developed in 90nm LP CMOS. The techniques developed include novelty in the local architecture with local read/write assist circuitry. VDD/2 pre-charged short local bit-lines with local sense amplifier enables charg...

Energy efficient computation becomes increasingly important for battery driven ubiquitous computing applications. To extend the battery life time while still meeting the performance demands, the designers face critical challenges in choosing the appropriate circuit topologies and low-power design techniques in order to optimally balance the power a...

Near-Threshold Circuits achieve ultra-low energy operating with significant performance improvement and noise immunity as compared to sub-threshold circuits. However, near-threshold circuit performance is highly sensitive to static and dynamic threshold voltage variations. This makes designing circuits for a target performance very difficult, and p...

Many signal processing applications demand for highly energy efficient flexible implementations. In this paper, we propose a novel Domain Specific Instruction-set Processor (DSIP) architecture template which is tuned to deploy in the targeted domain of on-line surveillance. The architecture, when implemented using a 40-nm CMOS standard cell library...

Power gating (PG) has emerged as an effective technique to reduce standby leakage power in portable devices where battery life time is vital. However, it comes at the cost of timing overhead which is a problem for most of the applications where real-time constraints exist. Designing efficient power gated circuits is very challenging problem due to...

Power consumption in digital systems, especially in portable devices, is a crucial design factor. Due to downscaling of technology, dynamic switching power is not the only relevant source of power consumption anymore as power dissipation caused by leakage currents increases. Even though power gating is a seemingly simple method for reducing the lea...

The forum provides an overview of complete portable medical device design. Tim Denison will share his thoughts on circuit design constraints and best practices in the regulated environment of medical device design. Bruno Murari will summarize the general requirements for a portable medical device from a product specification point of view.

Ultra low voltage operation promises to reduce power dissipation for wireless sensor network applications. Such ultra low voltage systems are likely to have many sub-systems operating at different frequencies and VDDs from super-threshold to sub-threshold. Synchronizers are needed to interface among these domains. However, VDD scaling rapidly degra...

Energy consumption in embedded systems is strongly dominated by instruction memory organizations. Based on this, any architectural enhancement introduced in this component will produce a significant reduction of the total energy bud-get of the system. Loop buffering is an effective scheme to reduce the energy consumption of the instruction memory o...

With new advances in ambulatory monitoring new challenges appear due to degradation in signal quality and limitations in hardware requirements. Existing signal analysis methods should be re-evaluated in order to adapt to the restrictive requirements of these new applications. With this motivation, we chose a robust beat detection algorithm and opti...

High efficiency and low power consumption are among the main topics in embedded systems today. For complex applications, off-the-shelf processor cores might not provide the desired goals in terms of power consumption. By optimizing the processor for the application, one can improve the computing power by introducing special purpose hardware units....

Wireless sensor nodes span a wide range of applications. This paper focuses on the biomedical area, more specifically on healthcare monitoring applications. Power dissipation is the dominant design constraint in this domain. This paper shows the different steps to develop a digital signal processing architecture for a single channel electrocardiogr...

A growing number of applications, often with firm or soft real-time requirements, are integrated on the same System on Chip, in the form of either hardware or software intellectual property. The applications are started and stopped at run time, creating different use-cases. Resources, such as interconnects and memories, are shared between different...

A growing number of applications, often with firm or soft real-time requirements, are integrated on the same System on Chip, in the form of either hardware or software intellectual property. The applications are started and stopped at run time, creating different use-cases. Resources, such as interconnects and memories, are shared between different...

This paper addresses the design challenges in wireless body area networks and gives an overview of recent technological achievements to tackle these challenges. It covers the areas of wireless communication, digital signal processing, sensing and read-out, and energy harvesting. In addition, this paper presents research platforms developed at IMEC/...

Impulse Radio-based Ultra-Wideband (UWB) technology is a strong candidate for the implementation of ultra low power air interfaces in low data rate sensor networks. A major challenge in UWB receiver design is the low-power implementation of the relatively complex digital baseband algorithms that are required for timing acquisition and data demodula...

This work presents a methodology for designing an ultra low power application specific instruction set processor. This paper shows the different steps to develop a digital signal processing architecture for a single channel ECG application assuming a system level power dissipation constraint of 100¿W. We follow a bottleneck driven approach based o...

Wireless sensor nodes span a wide range of applications. This paper focuses on the biomedical area, more specifically on healthcare monitoring applications. Power dissipation is the dominant design constraint in this domain. This paper shows the different steps to develop a digital signal processing architecture for a single channel electrocardiogr...

Multi-Processor System on Chip (MPSoC) platforms are becoming increasingly more heterogeneous and are shifting towards a more communication-centric methodology. Networks on Chip (NoC) have emerged as the design paradigm for scalable on-chip communication architectures. As the system complexity grows, the problem emerges as how to design and instant...

Multi-processor systems on chip (MPSoC) platforms are becoming increasingly more heterogeneous and are shifting towards a more communication-centric methodology. Networks on chip (NoC) have emerged as the design paradigm for scalable on-chip communication architectures. As the system complexity grows, the problem emerges as how to design and instan...

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Networks are a becoming a necessity to easily integrate multiple processors on a single chip. A crucial question here is whether it is good enough to reason about statistical performance as opposed to hard real-time performance constraints. Today’s processors often do not allow software design for hard real-time systems, caused by the design of the...

Growing complexity of multiprocessor systems on chip (MP-SoC) requires future communication resources that can only be met by highly scalable architectures. Networks-on-Chip (NoCs) offer this scalability and other advantages like modularity, quality-of-service (QoS), possibly smaller area footprint and lower power dissipation. Although many papers...

This paper presents a high performance FFT ASIP. The resulting programmable solution is scalable for the order of the FFT and capable of satisfying performance requirements of various OFDM wireless standards. The IEEE 802.15.3a ultra wideband OFDM - being the most time critical of these standards because of the computation of a 128-point FFT within...

The demands in terms of processing performance, communication bandwidth and real-time throughput of new generation mobile communication applications (mobile and base-stations) are much higher than today's programmable processing architectures can deliver. On the other hand standards and market uncertainties, nonrecurring engineering costs, and lack...