Jiang Xu

• Sichuan University

Chiplet technology has emerged as a promising solution to address the increasing demand for high-performance computing in light of the slowdown of Moore’s law. While chiplet-based multicore systems offer higher performance through heterogeneous integration, they also pose challenges for power delivery system (PDS) design. The integration of additio...

Detailed cycle-accurate simulation of multicore systems is naturally slow. Statistical simulation is one alternative that permits trading off simulation speed for accuracy. However, there is a lack of effective memory locality models for multicore applications. Hence, existing statistical simulators neglect data-sharing between threads. Additionall...

Silicon photonics is a promising technology for high-performance inter/intra-chip networks. Although chiplet technologies help to integrate photonic network with processors and memories, thermal reliability remains a major challenge for photonic networks. Thermal variations are common in chiplet-based systems. Due to thermo-optic effects, photonic...

We present a novel 3D-unfolding method based on Cosine-Sine-Decomposition (CSD) to enable an alternative arrangement of unitary blocks towards plane normal, which reduces the planar footprints of universal multiport interferometers exponentially.

To establish flatten networks and accomplish rapid and efficient communications in the future hyper-scale data centers, HERO, a high-radix optical switch based on integrated silicon photonics, is proposed in this work. The architecture of HERO, including the switch fabric, switch interface and switch controller, is described in detail. Two new swit...

This work proposes a novel loop-based optical neural network UONN capable of large-scale vector-matrix multiplications. Results show that UONN can achieve up to 6000 X higher energy efficiency than existing MZI-based neural network.

Silicon photonics is the leading candidate technology for high-speed and low-energy-consumption networks. Thermal and process variations are the two main challenges of achieving high-reliability photonic networks. Thermal variation is due to the heat issues created by application, floorplan, and environment, while process variation is caused by fab...

With the increasing popularity of data-intensive applications in data centers, the switching fabric in the internode network becomes significant. Silicon-photonic switching fabrics have a bright future in data centers, which offer high bandwidth, high energy efficiency, and low latency. However, integrating a high radix multistage switching fabric...

Minimizing energy consumption while satisfying the user-specified performance requirement is a primary design objective for mobile devices. To achieve this, off-the-shelf mobile devices are usually equipped with dynamic voltage and frequency scaling (DVFS)-enabled processors to tradeoff performance for energy reduction through online adjustment of...

Energy efficiency has become a critical design metric for high-performance systems. Various power management techniques have been proposed for the processor cores such as dynamic voltage and frequency scaling (DVFS), whereas few solutions consider the power losses suffered on the power delivery system (PDS), despite the fact that they have a signif...

Computing systems become increasingly heterogeneous by adopting domain-specific accelerators. While heterogeneity provides better trade-offs among performance, energy efficiency, and cost, it adds new dimensions to the already huge design space. Existing design exploration tools rely on time-based analysis. Simulating a heterogeneous computing syst...

Silicon photonic networks are revolutionizing computing systems by improving the energy efficiency, bandwidth, and latency of data movements. Optical modulators, such as microresonators and Mach-Zehnder Interferometers (MZIs), are the basic building blocks of silicon photonic networks. This work proposes a SPICE-compatible electro-optical co-simula...

Rack-scale computing systems are promising to undertake the emerging large-scale applications by distributing massive tasks to processing cores. The communication and coordination efficiency of these tasks and resources directly affect the system performance and energy consumption. Silicon photonic interconnects are expected to address the communic...

The advancement of silicon photonics promises integrated optical switches to provide high-bandwidth, low-latency and low-power communications in data centers. An optical switch’s loss limits its scale and affects the energy efficiency of the switch system. In this work, we present CLOSO, a cross-layer optimization framework, based on not only photo...

Maintaining high energy efficiency has become a critical design issue for high-performance systems. Many power management techniques have been proposed for the processor cores such as dynamic voltage and frequency scaling (DVFS). However, very few solutions consider the power losses suffered on the power delivery system (PDS), despite the fact that...

Rapidly evolving embedded applications continuously demand more functionalities and better performance under tight energy and thermal budgets, and maintaining high energy efficiency has become a significant design challenge for mobile devices. Learning-based methods are adaptive to dynamic conditions and show great potential for runtime power manag...

In recent years, optical interconnection networks have been proposed in order to achieve the ultrahigh bandwidth and low latency requirements for inter/intra-chip communication. In these optical interconection networks, series of basic optical elements are employed. Via these series of optical elements, the intrinsic crosstalk noise is generated. W...

The power delivery system (PDS), which plays a crucial role in guaranteeing the proper functionality of computing systems, has been a serious constraint on performance due to its significant power loss, especially for high-performance many-core processors. As the PDS design is usually optimized to provide power to the target chip at its best perfor...

As programs for microprocessor architectures, network-on-chip (NoC) traffic patterns are essential tools for NoC performance assessment and design exploration. The fidelity of NoC traffic patterns has profound influence on NoC studies. In this paper, we present a systematic traffic modeling and generation methodology and a traffic suite for efficie...

To accomplish high bandwidth and low latency communications among tens or even hundreds of nodes with low power consumption, DRAGON, a new integrated high-radix strictly non-blocking optical switching fabric, is proposed in this work. The topology and routing algorithm of DRAGON are discussed, and a formal proof for the strictly non-blocking proper...

Anti‑nicotinic acetylcholine receptor (nAChR) antibody in myasthenia gravis (MG) usually refers to that against the extracellular domain (ECD) of nAChR. However, growing evidence has indicated that there also exists the nAChR antibody against the nAChR cytoplasmic loop (CL) in patients with MG. Some studies have demonstrated that the anti‑CL antibo...

The memory wall problem is due to the imbalanced developments and separation of processors and memories. It is becoming acute as more and more processor cores are integrated into a single chip and demand higher memory bandwidth through limited chip pins. Optical memory interconnection network (OMIN) promises high bandwidth, bandwidth density, and e...

The number of chip pins is limited due to the cost and reliability issues of sophisticated packages, and it is predicted that the chip pin count will be overstretched to satisfy the requirements of both power delivery and memory access. The gap between the achievable pin count and the demand will increase as the technology scales, due to the increa...

We model and compare a novel space switch, FODON, with wavelength selective switch AWGR in terms of latency, throughput and energy consumption. Both the single wavelength scheme and multiple wavelengths scheme are evaluated.

Software-defined servers provide high flexibility and customizablility with low power consumption. To satisfy the ultrahigh bandwidth requirement of the interconnection of these servers, integrated optical switch networks, based on the recent development of silicon photonics, are promising candidates. In this study, we present a family of floorplan...

Power gating (PG) is one of the most effective techniques to reduce the leakage power in multiprocessor system-on-chips (MPSoCs). However, the power-mode transition during the PG period of an individual processing unit (PU) will introduce serious power/ground (P/G) noise to the neighboring PUs. As technology scales, the P/G noise problem becomes a...

Recently, interchip/intrachip optical interconnection networks have been proposed for ultrahigh-bandwidth and low-latency communications. These networks employ the microresonators (MRs) to modulate, direct, or detect the optical signal. However, utilized MRs suffer from intrinsic crosstalk noise and signal power loss, degrading the network efficien...

With the fast development of inter/intra-chip optical interconnects, the gap between the data rates of electrical interconnects and optical interconnects is continuously increasing. Electrical-optical (E-O) interfaces and optical-electrical (O-E) interfaces are a pair of components that convert data between parallel electrical interconnects and ser...

Recent advances in the computing industry towards multiprocessor technologies shifted the dominant method of performance increase from frequency scaling to parallelism. Due to its huge design space, evaluating candidate multicore architectures in early design stages, when the number of variables is at its maximum, is challenging. Simulation plays a...

The design of power delivery system plays a crucial role in guaranteeing the proper functionality of many-core pro-cessor systems. The power loss suffered on power delivery has become a salient part of total power consumption, and the energy efficiency of a highly dynamic system has been significantly chal-lenged. Being able to achieve a fast respo...

Design of power delivery system has great influence on the power management in many-core processor systems. Moving voltage regulators from off-chip to on-chip gains more and more interest in the power delivery system design, because it is able to provide fine-grained dynamic voltage scaling. Previous works are proposed to implement power efficient...

As transistor density continues to increase with the advent of nanotechnology, reliability issues raised by more frequently appeared soft errors are becoming even more critical to the next-generation multiprocessor systems. In this paper, we present a systematic approach to address the soft-error problem in multiprocessor system-on-chip with the co...

With the fast development of processor chips, power-efficient, high-bandwidth, and low-latency interchip interconnects become more and more important. Studies show that the bandwidth of traditional parallel interconnects with low I/O clock frequencies will become bottlenecks in the near future. To solve this problem, two types of high-bandwidth int...

Power gating is one of the most effective techniques to reduce the leakage power in multiprocessor system-on-chips (MPSoCs). However, the power-mode transition during the power gating period of an individual processing unit will introduce serious power/ground (P/G) noise to the neighboring processing units. As technology scales, the P/G noise probl...

Manycore processor system is becoming an attractive platform for applications seeking both high performance and high energy efficiency. However, huge communication demands among cores, large power density, and low process yield will be three significant limitations for the scalability of future manycore processors. Breaking a large chip into multip...

Chip I/O pins are an increasingly limited resource and significantly affect the performance, power and cost of multicore processors. Optical interconnects promise low power and high bandwidth, and are potential alternatives to electrical interconnects. This work systematically developed a set of analytical models for electrical and optical intercon...

The Network-on-chip (NoC) based multiprocessor system-on-chip (MPSoCs) is becoming a promising architecture to meet modern applications' ever-increasing demands for computing capability under limited power budget. NoC traffic patterns are essential tools for NoC performance assessment and architecture design exploration. In this paper, we present a...

Basic photonic devices in inter- and intra-chip optical networks suffer from inevitable power loss and crosstalk noise. Incoherent crosstalk introduces quick power fluctuations, while coherent crosstalk varies the optical power of the optical signal in optical interconnection networks (OINs). As a result, the accumulative crosstalk in large scale O...

In order to obtain bioactive α-bungarotoxin (αBtx) using recombinant protein technique, a codon-optimized synthetic gene was expressed in fusion with the N-terminal 10-His-tag and C-terminal Strep-tag in Escherichiacoli. Further optimization through site-directed mutagenesis enabled moderate expression of the protein without the N-terminal His-tag...

Optical networks-on-chip (ONoCs) have shown the potential to be substituted for electronic networks-on-chip (NoCs) to bring substantially higher bandwidth and more efficient power consumption in both onand off-chip communication. However, basic optical devices, which are the key components in constructing ONoCs, experience inevitable crosstalk nois...

Optical networks-on-chip (ONoCs) using wavelength-division multiplexing (WDM) technology have progressively attracted more and more attention for their use in tackling the high-power consumption and low bandwidth issues in growing metallic interconnection networks in multiprocessor systems-on-chip. However, the basic optical devices employed to con...

Myasthenia gravis is a typical acetylcholine receptor (AChR) antibody-mediated autoimmune disease in which thymus frequently presents follicular hyperplasia or thymoma. It is now widely accepted that the thymus is probably the site of AChR autosensitization and autoantibody production. However, the exact mechanism that triggers intrathymic AChR ant...

Multiprocessor systems-on-chip show a trend toward integration of tens and hundreds of processor cores on a single chip. With the development of silicon photonics for short-haul optical communication, wavelength division multiplexing (WDM)-based optical networks-on-chip (ONoCs) are emerging on-chip communication architectures that can potentially o...

Microresonators have been utilized to construct optical interconnection networks. One of the drawbacks of these microresonators is that they suffer from intrinsic crosstalk noise and power loss, resulting in Signal-to-Noise Ratio (SNR) reduction and system performance degradation at the network level. The novel contribution of this paper is to syst...

Network-on-chip (NoC) based multiprocessor system-on-chips (MPSoCs) have been proposed as promising architectures to meet modern applications' ever-increasing demands for computing capability under limited power budget. Understanding the behaviors of MPSoC applications is the key to design MPSoCs under tight power and performance constraints. In th...

Chip multiprocessor (CMP) is becoming an attractive platform for applications seeking both high performance and high energy efficiency. In large-scale CMPs, the communication efficiency among cores is crucial for the overall system performance and energy consumption. In this article, we propose a ring-based optical network-on-chip, called SUOR, to...

Chip multiprocessor (CMP) is becoming increasingly popular in the processor industry. Efficient network-on-chip (NoC) that has similar performance to the processor cores is important in CMP design. Fat-tree-based on-chip network has many advantages over traditional mesh or torus-based networks in terms of throughput, power efficiency, and latency....

Introduction Human myasthenia gravis (MG) is an autoimmune disorder of the neuromuscular system. Experimental autoimmune myasthenia gravis (EAMG) is a well-established animal model for MG that can be induced by active immunization with the Torpedo californica-derived acetylcholine receptor (AChR). Due to the expensive cost of purifying AChR from To...

Photonic devices are widely used in optical networks-on-chip (ONoCs) and suffer from crosstalk noise. The accumulative crosstalk noise in large scale ONoCs diminishes the signal-to-noise ratio (SNR), causes severe performance degradation, and constrains the network scalability. For the first time, this paper systematically analyzes and models the w...

As transistor density continues to increase with the advent of nanotechnology, reliability issues raised by the more frequent appearance of soft errors are becoming critical for future embedded multiprocessor systems design. State-of-the-art techniques for soft error protections targeting multiprocessor systems result either high chip cost and area...

Design of power delivery system has great influence on the power management in many-core processor systems. Moving voltage regulators from off-chip to on-chip gains more and more interest in the power delivery system design, because it is able to provide fast voltage scaling and multiple power domains. Previous works are proposed to implement power...

By integrating multiple processing units (PUs) and memories on a single chip, multiprocessor system-on-chip (MPSoC) can provide higher performance per energy and lower cost per function to applications with growing complexity. On the other hand, shrinking feature sizes and reducing power supply voltages also make MPSoCs more susceptible to various...

The efficiency of collaboration among processors is a critical design metric for multiprocessor systems-on-chip (MPSoCs). It is the communication architecture that determines the collaboration efficiency on the hardware side. Optical NoCs, which are based on optical interconnects and optical routers, offer a new approach to empowering ultra-high ba...

Crosstalk noise is an intrinsic characteristic as well as a potential issue of photonic devices. In large scale optical networks-on-chips (ONoCs), crosstalk noise could cause severe performance degradation and prevent ONoC from communicating properly. The novel contribution of this paper is the systematical modeling and analysis of the crosstalk no...

Network-on-chip (NoC) can improve the performance, power efficiency, and scalability of multiprocessor system-on-chip (MPSoC). Optical NoCs, which are based on CMOS-compatible optical waveguides and microresonators, have significant bandwidth and power advantages over metallic interconnects. We propose a low-cost mesh-based hybrid optical-electroni...

Optical networks-on-chip (ONoCs) are emerging communication architectures that can potentially offer ultrahigh communication bandwidth and low latency to multiprocessor systems-on-chip (MPSoCs). In addition to ONoC architectures, 3-D integrated technologies offer an opportunity to continue performance improvements with higher integration densities....

We demonstrate a five-port optical router that is suitable for large-scale photonic networks-on-chip. The optical router is designed to passively route the optical signal travelling in one direction and actively route the optical signal making a turn. In the case that an XY dimension-order routing is used, the passive routing feature guarantees tha...

By integrating multiple processing units and memories on a single chip, multiprocessor system-on-chip (MPSoC) can provide higher performance per energy and lower cost per function to applications with growing complexity. In order to maintain the power budget, power gating technique is widely used to reduce the leakage power. However, it will introd...

Multiprocessor systems-on-chip (MPSoCs) make an attractive platform for high-performance applications. Networks-on-chip (NoCs) can improve the on-chip communication bandwidth of MPSoCs. However, traditional metallic interconnects consume a significant amount of power to deliver even higher communication bandwidth required in the near future. Optica...

Network-on-chip (NoC) can improve the performance, power efficiency, and scalability of chip multiprocessors (CMPs). However, traditional NoCs using metallic interconnects consume a significant amount of power to deliver high communication bandwidth required in the near future. Optical NoCs are based on CMOS-compatible optical waveguides and optica...

Autoantibody-induced complement activation, which causes disruption of the postsynaptic membrane, is recognized as a key pathogenic factor in myasthenia gravis (MG). Therefore, specific targeting of complement inhibitors to the site of complement activation is a potential therapeutic strategy for treatment of MG. We assessed expression of single-ch...

We propose 3D mesh-based optical network-on-chip (ONoC) based on a novel low-cost 6×6 optical router, and quantitatively analyze thermal effects on the 3D ONoC. Evaluation results show that with the traditional thermal tuning technique using microheater, the average power efficiency of the 3D ONoC is about 2.7pJ/bit, while chip temperature varies s...

Optical network-on-chip (ONoC) can be used as the communication backbone for high performance chip multiprocessors (CMPs). Fat tree based ONoC shows high throughput, small delay and low power consumption. However, the traditional floorplan design of fat tree based ONoC has a large number of waveguide crossings because of the fat tree topology. In t...

Networks-on-chip (NoCs) are emerging as a key on-chip communication architecture for multiprocessor systems-on-chip (MPSoCs). Optical communication technologies are introduced to NoCs in order to empower ultra-high bandwidth with low power consumption. However, in existing optical NoCs, communication locality is poorly supported, and the importance...