Jens Kargaard Madsen

(Aarhus University · Department of Engineering

In spintronic-based neuromorphic computing systems (NCS), the switching of magnetic moment in a magnetic tunnel junction (MTJ) is used to mimic neuron firing. However, the stochastic switching behavior of the MTJ and process variations effect lead to a significant increase in stimulation time of such NCSs. Moreover, current NCSs need an extra phase...

In this paper, a high-speed and low-power latched comparator in a 65-nm CMOS process is presented. In our proposed structure, a latched circuit with an adjusted delayed-clock with no static power consumption is added to the conventional latch-type comparator in order to enhance the clock frequency and reduce the power consumption and the delay time...

A combination of semiconductor integrated circuits (IC) and a dense array of scaled magnetic tunnel junctions (MTJ) makes promising Spin-Transfer Torque Random Access Memory (STT-RAM). This emerging memory minimizes the leakage power consumption and provides a high density at scaled technologies. In this paper, we propose a novel non-destructive se...

A novel sub-threshold 9 T Static Random Access Memory (SRAM) cell designed and simulated in 14-nm FinFET technology is proposed in this paper. The proposed 9 T-SRAM cell offers an improved access time in comparison to the 8 T-SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 2...

With the fast progress in miniaturization of sensors and advances in micromachinery systems, a gate has been opened to the researchers to develop extremely small wearable/implantable microsystems for different applications. However, these devices are reaching not to a physical limit but a power limit, which is a critical limit for further miniaturi...

This paper presents a low-power instrumentational amplifier (IA) design for EEG signal acquisition for seizure detection. The proposed structure provides a power per channel of 0.92 µW at supply voltage of 0.8 V. Due to the use of buffer structures and impedance boosting loops in the proposed design, the input impedance has reached up to 160 GΩ and...

Spin-transfer torque random access memory (STT-RAM) has emerged as an attractive candidate for future nonvolatile memories. It advantages the benefits of current state-of-the-art memories including high-speed read operation (of static RAM), high density (of dynamic RAM), and nonvolatility (of flash memories). However, the write operation in the 1T-...

SRAM operation at subthreshold/weak inversion region provides a significant power reduction for digital circuits. SRAM arrays which contribute to a large amount of power consumption for the processors in sub-100 nm technologies, however, cannot benefit from subthreshold operation. To this end, new SRAM technique on the circuit or architecture level...

In this paper, a new write assist technique is proposed to improve the write characteristics of 1T-1MTJ STT-RAM bitcell through a symmetric write operation. This is done by applying a negative voltage to the bitline during write `1' operation. The proposed technique is compared with the best previously proposed techniques. The simulation results us...

In this paper, we propose a new sub-threshold 9T-Static Random Access Memory (SRAM) cell in 14 nm FinFET technology by which the access time of the memory cell is improved by at least 30 percent compared to the standard 8T-SRAM cell. Furthermore, the leakage current of the proposed SRAM cell is reduced by an assisting circuit. Simulation results sh...

Spin-transfer torque random access memory (STT-RAM) has emerged as an attractive candidate for future non-volatile memories. However, the write operation in 1T-1MTJ STT-RAM bit-cells is asymmetric and stochastic which leads to high energy consumption and long latency. In this paper, a new write assist technique is proposed to terminate the write op...

This paper presents a novel subthreshold 8T-SRAM for ultra-low power applications. The proposed SRAM cell improves write margin by at least 22% to the standard 6T-SRAM cell at supply voltage of 1V compared. Furthermore, read static noise margin is improved by at least 2.2X compared to the standard 6T-SRAM cell. Although by the use of the proposed S...

In this paper, FinFET devices are compared to bulk CMOS technology by looking at the characteristics of both devices and their challenges in nano-scale regimes. The effects of process variations on these devices along with the effect of device parameters on their characteristics are explored. Both FinFET and CMOS devices are used in 6T and 8T-SRAM...

In this paper, a novel 7T-SRAM cell for ultra-low power applications is proposed. The proposed SRAM cell is fully functional at subthreshold voltages down to VDDmin=200mV. In this technique, separate read/write bitlines and wordlines are used that makes read and write operation independent. The 7T-SRAM cell proposed in this paper, improves static r...

In this paper, a multi-level wordline driver scheme is presented to improve 6T-SRAM read and write stability. The proposed wordline driver generates a shaped pulse during the read mode and a boosted wordline during the write mode. During read, the shaped pulse is tuned at nominal voltage for a short period of time, whereas for the remaining access...

In this paper, new flip-flop topologies for low power and high-speed digital designs are presented. A novel technique is used to generate a special clock-pulse wave (internally or externally) for flip-flop circuits. This technique shows better characteristics compared to existing techniques in terms of delay and power. The generated pulse is applie...

In this paper, a multi-level wordline driver scheme is presented to improve SRAM read and write stability while lowering power consumption during hold operation. The proposed circuit applies a shaped wordline voltage pulse during read mode and a boosted wordline pulse during write mode. During read, the applied shaped pulse is tuned at nominal volt...

The paper presents ASE-BAN, a wireless Body Area Network (BAN) developed at Aarhus University School of Engineering (ASE). ASE-BAN is a modular platform enabling research in the healthcare area and allowing real-life experiments with real users. The paper presents requirements, architecture and implementation of a hardware platform consisting of di...

This paper describes the design and implementation of a high-speed GaAs asynchronous transfer mode (ATM) mux-demux ASIC (AMDA) which is the core LSI circuit in a high-speed ATM add-drop unit (ADU). This unit is used in a new distributed ATM multiplexing-demultiplexing architecture for broadband switching systems. The ADU provides a cell-based inter...

Miniature Body Area Networks used in health care support greater mobility to patients and reduces actual hospitalization. This paper presents the preliminary implementation of a wireless body area network gateway. It is designed to implement the gateway functionality between sensors/actuators attached to the body and a host server application. The...

This paper describes a Gallium Arsenide logic family called Ternary Source Coupled Fet Logic (TSCFL) that provides ternary logic elements for use in Delay Insensitive (Dl) circuits. These Dl circuits are self-timed and operate regardless of delays in wires, logic and register elements. By using ternary levels, only one wire is necessary to implemen...