Jean-Didier Legat

Jean-Didier Legat
Université Catholique de Louvain - UCLouvain | UCLouvain · Louvain School of Engineering

About

178
Publications
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Introduction

Publications

Publications (178)
Conference Paper
In an attempt to follow biological information representation and organization principles, the field of neuromorphic engineering is usually approached bottom-up, from the biophysical models to large-scale integration in silico. While ideal as experimentation platforms for cognitive computing and neuroscience, bottom-up neuromorphic processors have...
Preprint
Full-text available
In an attempt to follow biological information representation and organization principles, the field of neuromorphic engineering is usually approached bottom-up, from the biophysical models to large-scale integration in silico. While ideal as experimentation platforms for cognitive computing and neuroscience, bottom-up neuromorphic processors have...
Article
Recent trends in the field of neural network accelerators investigate weight quantization as a means to increase the resource- and power-efficiency of hardware devices. As full on-chip weight storage is necessary to avoid the high energy cost of off-chip memory accesses, memory reduction requirements for weight storage pushed toward the use of bina...
Preprint
Recent trends in the field of neural network accelerators investigate weight quantization as a means to increase the resource- and power-efficiency of hardware devices. As full on-chip weight storage is necessary to avoid the high energy cost of off-chip memory accesses, memory reduction requirements for weight storage pushed toward the use of bina...
Preprint
Recent trends in the field of neural network accelerators investigate weight quantization as a means to increase the resource- and power-efficiency of hardware devices. As full on-chip weight storage is necessary to avoid the high energy cost of off-chip memory accesses, memory reduction requirements for weight storage pushed toward the use of bina...
Article
Shifting computing architectures from von Neumann to event-based spiking neural networks (SNNs) uncovers new opportunities for low-power processing of sensory data in applications such as vision or sensorimotor control. Exploring roads toward cognitive SNNs requires the design of compact, low-power and versatile experimentation platforms with the k...
Article
In this paper, we propose pulse-triggered flip-flops (pulsed-FF) and register file in 28 nm Ultra-Thin-Body-and-Box Fully-Depleted-Silicon-on-Insulator (UTBB-FDSOI) technology, dedicated to ultra-wide voltage range (UWVR) operation. A pulsed-FF composed of a latch and a pulse generator offers potential power/performance/area (PPA) advantages over t...
Conference Paper
Single-Event Effects are an increasingly important issue in electronic circuits due to technology scaling, efficient error detection schemes are thus required for circuits dedicated to radiative environments, such as in space applications. This work shows that the widespread spatial and temporal redundancy schemes exhibit widely different performan...
Conference Paper
Full-text available
In this paper, the minimum operating voltage of master-slave flip-flops made in advanced fully-depleted silicon on insulator (FDSOI) technology, is studied through silicon measurements. A shift register of 1024 master-slave flip-flops has been fabricated in 28nm FDSOI technology in order to study the minimum operating voltage with respect to a wide...
Conference Paper
Full-text available
In the context of wireless sensor nodes for the Internet-of-Things, there is a need for low-power high-performance computing cores for video monitoring applications. In this paper we present a custom 50MHz 32-bit microcontroller running at 0.37V built on a 65nm LP/GP CMOS process. Part of an energy-harvesting SoC with on-chip CMOS imager, it featur...
Article
In this paper, a robust and energy efficient pulse-triggered flip–flop (pulsed-FF) architecture dedicated to ultra-low voltage (ULV) operations is proposed. The main innovation lays in the architecture of the pulse generator (PG) of the pulsed-FF. It allows designers to reach a robust pulsed-FF architecture without dramatic area and energy penalty....
Conference Paper
So far, pulse-triggered flip-flops (pulsed-FFs) are mainly used in high-performance digital circuits, thanks to their small data-to-output delay. However, they suffer from a poor robustness to local variations occurring at ultra-low-voltage (ULV). Thanks to an innovative pulse generator, the operability of an energy-efficient pulsed-FF was validate...
Conference Paper
In this paper, a robust and energy efficient pulse generator (PG), dedicated to pulse-triggered flip-flops (pulsed-FFs) in ultra-wide voltage range (UWVR) applications, is proposed. Pulsed-FFs are promising candidate for high-speed and low-power applications, thanks to their small data-to-output delay and their shareable PG. However, UWVR circuits...
Conference Paper
Full-text available
The vision of the Internet-of-Things (IoT) calls for the deployment of trillions of wireless sensor nodes (WSNs) in our environment. A sustainable deployment of such a large number of electronic systems needs to be addressed with a Design-for-the-Environment approach. This requires minimizing 1) the embodied energy and carbon footprint of the WSN p...
Conference Paper
The De Bruijn topology, due to its interesting features such as a small minimal path, a small average latency and a small average number of hops, is a promising alternative topology to mesh-based NoCs for low-power applications. However, these advantages strongly depend on the efficiency of the routing algorithm in presence of congestion. This pape...
Conference Paper
Full-text available
In this paper, a new metric to compute the setup time of pulse-triggered flip-flops (pulsed-FFs) is proposed. With the emergence of new technologies, digital circuits are pushing towards high-speed and energy efficient modes. Setup time is an essential aspect of the timing constraints of a synchronous digital circuit. It is a key parameter to deter...
Conference Paper
Full-text available
Integrated circuits for wireless sensor nodes (WSNs) targeting the Internet-of-Things (IoT) paradigm require ultralow-power consumption for energy-harvesting operation and low die area for low-cost nodes. As the IoT calls for the deployment of trillions of WSNs, minimizing the carbon footprint for WSN chip manufacturing further emerges as a third t...
Conference Paper
With the advent of mobile electronics requiring ever more computing power from a limited energy supply, there is a need for efficient systems capable of maximizing this ratio. Architectural enhancements must therefore be designed to enable high performance, all the while maintaining the power advantage. The technique proposed in this paper allows t...
Conference Paper
With the increasing complexity and functionality of Real-Time embedded applications, Multiprocessor System-on-chip “MPSoC” offers the best tradeoffs in computation performances and power consumption. Designing MPSoC projects is time consuming and, often requires several competences and steps, spanning from hardware architecture to mapping applicati...
Article
The development of sustainable and durable ultra-low-power SoC calls for flexibility integration in the design flow. Reconfigurable logic circumvents the intrinsic low speed performances of software processing in microcontrollers but FPGA fabrics to be embedded suffer from a high power overhead compared to dedicated ASICs. We show that, by combinin...
Article
IntroductionImpact of Technology Scaling on Subthreshold MOSFET CharacteristicsScaling Trend of the Minimum-Energy PointPractical Energy of Nanometer ULV Circuits under Robustness and Timing ConstraintsTechnology/Circuit Methodology and Roadmap for ULV Design in the Nanometer EraConclusion References
Article
The vision of the Internet of Things with ambient intelligence calls for the deployment of up to a trillion connected wireless sensor nodes (WSNs). Minimizing the carbon footprint of each node is paramount from the sustainability perspective. In ultra-low-power applications, the life-cycle carbon footprint results from a complex balance between bot...
Chapter
Professional embedded electronic applications are found in military, security, or high reliability systems like in avionics and aerospace. They have to meet specific requirements, and they are produced in low or even very low volumes. In this field of applications, telecommunication applications have to face a diversity issue due to the high number...
Article
A Hybrid router architecture for Networks-on-Chip “NoC” is presented, it combines Spatial Division Multiplexing “SDM” based circuit switching and packet switching in order to efficiently and separately handle both streaming and best-effort traffic generated in real-time applications. Furthermore the SDM technique is combined with Time Division Mult...
Conference Paper
Wireless sensor node platforms are very diversified and very constrained, particularly in power consumption. When choosing or sizing a platform for a given application, it is necessary to be able to evaluate in an early design stage the impact of those choices. Applied to the computing platform implemented on the sensor node, it requires a good und...
Conference Paper
In embedded systems, achieving good performances for signal processing applications is crucial for power management. Good compilation is required to have maximal use of the available processing capabilities. Compiling for communication-exposed architectures such as ADRES, TRIPS and Wavescalar is however a complex task. Dataflow graphs are mapped on...
Conference Paper
This paper presents a mechanism to decrease the congestion on TDM networks handling both Best Effort and Guaranteed Throughput traffic. The mechanism consists of an algorithm which gives an optimal Time Slot to begin transactions between source and destination, thus maximising the probability of successfully reserving a path through the network, to...
Conference Paper
This paper proposes a circuit-switched router which combines Spatial Division Multiplexing “SDM” and Time Division Multiplexing “TDM” in order to increase path diversity in the router while sharing channels among multiple connections. In this way, the probability of establishing paths through the network is increased, thereby significantly reducing...
Article
Full-text available
An important challenge associated with the current massive deployment of Radio Frequency Identification solutions is to provide security to passive tags while meeting their micro Watt power budget. This can either be achieved by designing new lightweight ciphers, or by proposing advanced low-power implementations of standard ciphers. In this paper,...
Conference Paper
In this paper we propose a hybrid network-on-chip which combines Spatial Division Multiplexing “SDM”-based circuit switching and packet switching in order to efficiently and separately handle streaming and best-effort traffics generated by real-time applications. The SDM technique is used in circuit-switched sub-network in order to increase path di...
Conference Paper
Full-text available
A Hybrid router architecture for Networks-on-Chip “NoC” is presented, it combines Spatial Division Multiplexing “SDM” based circuit switching and packet switching in order to efficiently and separately handle both streaming and best-effort traffic generated in real-time applications. Furthermore the SDM technique is combined with Time Division Mult...
Article
Full-text available
Subthreshold operation of digital circuits enables minimum energy consumption. In this article, we observe that minimum energy E min of subthreshold logic dramatically increases when reaching 45nm CMOS node. We demonstrate by circuit simulation and analytical modeling that this increase comes from the combined effects of variability, gate leakage,...
Conference Paper
Full-text available
Ultra-low-voltage operation efficiently reduces energy consumption of digital circuits. However, subthreshold MOSFET behavior completely modifies the impact of process, voltage and temperature variations. This paper demonstrates that negative Celsius temperatures are highly detrimental to ultra-low-voltage logic, even more than process variations....
Conference Paper
Full-text available
The power efficiency of an HMCP heavily depends on the architecture of its processor cores. It is thus very important to choose it carefully. When comparing processing architectures for their use in a many-core platform, one must evaluate its IPC, but also its power and area. Precise power and area evaluations can only be done with real implementat...
Article
In this paper, we first propose a new structure of a hybrid full adder, namely, the branch-based logic and pass-transistor (BBL-PT) cell, which we implemented by combining branch-based logic and pass-transistor logic. Evolution of the proposed cell from its original version to an ultralow-power (ULP) cell is described. Quantitative comparisons of t...
Conference Paper
In ultra-low-power applications with long standby periods, power-gating technique can be combined with sub-threshold operation to minimize energy. However, in nanometer technologies, we show in this paper that the introduction of the sleep transistor threatens subthreshold circuit robustness because of noise margin degradation. An increase in V<sub...
Conference Paper
Since applications can generate both streaming and best effort traffics, there is then a need for an on-chip network to provide QoS for streaming traffic and to guarantee packets delivery without loss for best effort traffic. Instead of handling both streaming and best-effort traffic in a circuit or packet switched network, which often leads to a c...
Conference Paper
Real-Time applications generate both streaming and best-effort traffics. The on-chip interconnection network for these applications must be able to guarantee Quality of Service "QoS" for streaming traffic and no packet loss for best-effort traffic. In order to efficiently handle both streaming and best-effort traffic, we propose in this paper a hyb...
Conference Paper
Undoped devices in FD SOI technology provides improved switching speed to ULP logic, while keeping ultra-low leakage. Measurement results in 0.15 mum FD SOI technology show that it can be used to build 500 kHz digital circuits for sensing applications, with 0.95 V noise margins at 1.5 V thanks to the hysteresis property of ULP logic. The record mea...
Article
Full-text available
Subthreshold logic is an efficient technique to achieve ultralow energy per operation for low-to-medium throughput applications. In this paper, the interests and limitations of technology scaling for subthreshold logic are investigated from 0.25 mum to 32 nm nodes. Scaling to 90/65 nm nodes is shown to be highly desirable for medium-throughput appl...
Conference Paper
In this paper, we present the SEE characterization of an 80C51 microcontroller optimized for high temperature and low-power applications. Its microarchitecture has been completely redesigned with deep low-power optimizations. It has been manufactured in a 1μm SOI process with tungsten metallization layers ensuring a high sustained operating tempera...
Conference Paper
Today, available embedded automotive systems offer valuable services and allow building highly added value applications in transports and logistics. However the fast changing needs in this market have added more constraints on the design process of theses systems. Making such systems easy to upgrade according to the latest technologies, new data so...
Conference Paper
Full-text available
In this paper, we observe that minimum energy Emin of subthreshold logic dramatically increases when reaching 45nm node. We demonstrate by circuit simulation and analytical modeling that this increase comes from the combined effects of variability, gate leakage and DIBL. We then investigate the new impact of MOSFET parameters on Emin in nanometer t...
Conference Paper
Full-text available
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show that technology flavor and Vt selections shift minimum-energy point to different operating frequencies, thereby enabling minimum energy in either low- or mid-performance ap...
Article
Full-text available
Signal and image processing applications require a lot of computing resources. For low-volume applications like in professional electronics applications, FPGA are used in combination with DSP and GPP in order to reach the performances required by the product roadmaps. Nevertheless, FPGA designs are static, which raises a flexibility issue with new...
Article
For ultra-low-power applications, digital integrated circuits may operate at low frequency to reduce dynamic power consumption. At high temperature, the power consumption of such circuits is completely dominated by static power dissipation due to leakage currents. In this contribution, we propose a new logic style, namely ultra-low-power (ULP) logi...
Conference Paper
Full-text available
Over the last decade, the design of ultra-low-power digital circuits in subthreshold regime has been driven by the quest for minimum energy per operation. In this contribution, we observe that operating at minimum-energy point is not straightforward as design constraints from real-life applications have an important impact on energy. Therefore, we...
Conference Paper
The improved immunity of FD SOI technology against short-channel effects has been shown to offer a great interest for subthreshold logic in terms of delay and energy per operation at medium throughputs (108 Op/s). Moreover, the combination of an undoped channel with a metal gate extends this benefit to lower throughputs by a reduction of the minimu...
Conference Paper
Subthreshold circuits exhibit ultra-low energy per operation at the expense of increased delay. In this contribution, the impact of technology scaling on digital subthreshold circuits is investigated. Migrating from 0.25-mum to 32-nm node is shown to considerably lower the energy consumption of a subthreshold 8x8-bit RCA multiplier. When reaching t...
Conference Paper
Leakage current is the main source of power dissipation in low-frequency digital circuits implemented in deep submicron processes. This contribution introduces a novel active-mode leakage reduction technique for Ultra-Low-Power (ULP) low-frequency applications. It is based on the ULP CMOS logic style achieving negative-V GS self-biasing. ULP logic...
Conference Paper
With the increasing capacity of FPGAs following the Moore's law, it is possible to build in a single FPGA, a large system on chip (SoC) composed by several cores. Their performances depend strongly on their interconnection structure. Traditional and hierarchical busses are not suitable to be used. The Networks on Chip (NoC), due to their characteri...
Conference Paper
As one major challenge today in transport is the reduction of greenhouse gas emission and the decrease of fuel consumption, the development of methods for the optimal use of a vehicle and fuel savings becomes then mandatory. Fleet management is especially concerned by this problem. Moreover, for the EUR05 norm to be fully efficient, the driver beco...
Conference Paper
Full-text available
This paper presents the RECOPS project that aims to study the use of reconfiguration in military applications. The project explores the new potentials and possibilities offered by reconfigurable components like FPGA. It identifies specificities related to the use of this technology in military applications and proposes solutions to support them. Sp...
Article
This paper describes two new dynamic differential self-timed logic families that can be used either to implement low-power security components or low-power high-speed self-timed circuits. Electrical simulations in 0.13μm partially depleted (PD) SOI CMOS under a Vdd of 1.2V have shown that the substitution box (S-box), a module of the Khazad cipher...
Conference Paper
As the trend in reconfigurable electronics goes towards strong integration, FPGA devices are becoming more and more interesting. They are already used for safety-critical applications such as avionics [9]. Latest FPGA's also en-able new techniques such as dynamic partial reconfigura-tion (DPR), allowing new possibilities in terms of perfor-mance an...
Conference Paper
Full-text available
Threshold logic is an interesting alternative to Boolean logic in the field of high-performance arithmetic circuits. It offers reduced logic depth and gate count. A competitive implementation of threshold logic uses monostable-bistable transition logic elements (MOBILE). The aim of this contribution is to evaluate a specific implementation of MOBIL...
Article
Full-text available
For the last ten years, security of integrated circuits has attracted a greater attention from the cryptographic community. Several sources of information leakage within the circuits have been emphasized. Power consumption based attacks have been mounted successfully against various types of circuits like ASIC, smartcards or FPGA. To counter them,...
Conference Paper
Full-text available
Out-of-order execution significantly increases the performance of superscalar processors. The out-of-order execution mech- anism is, however, energy-inefficient, which inhibits scaling superscalar processors to high issue widths and large instruc- tion windows. In this paper, we build on the observation that between 19% and 36% of the instructions...
Conference Paper
Full-text available
This paper presents the RECOPS project that aims to study the use of reconfiguration in military applications. The project explores the new potentials and possibilities offered by reconfigurable components like FPGA. It identifies specificities related to the use of this technology in military applications and proposes solutions to support them. Sp...
Article
Full-text available
We present an efficient implementation for the current-mode radix-2 signed-digit full adder (SDFA). It is based on negative-differential-resistance (NDR) MOS structures. Simulations have been carried out using a 0.13-μm SOl CMOS technology. Since it uses dynamic current-mode logic (DyCML) comparators and features a dual-rail structure, the NDR-MOS...
Article
Full-text available
The image compression standard JPEG 2000 proposes a large set of features that is useful for today's multimedia applications. Unfortunately, it is much more complex than older standards. Real-time applications, such as digital cinema, require a specific, secure, and scalable hardware implementation. In this paper, a decoding scheme is proposed with...
Conference Paper
Full-text available
This paper proposes different low-cost coprocessors for public key authentication on 8-bit smart cards. Elliptic curve cryptography is used for its efficiency per bit of key and the Elliptic Curve Digital Signature Algorithm is chosen. For this functionality, an area constrained coprocessor is probably the best approach to perform the most computer...
Article
A new logic style called low-swing current mode logic (LSCML) is presented. It features a dynamic and differential structure and a low-swing current mode operation. The LSCML logic style may be used for hardware implementation of secure smart cards against differential power analysis (DPA) attacks but also for implementation of self-timed circuits...
Conference Paper
Full-text available
In this paper, we present a low power high temperature 80C51 microcontroller. The low power optimizations are applied at gate and architectural level, by using extensive clock and data gating, and by completely redesigning the micro-architecture. We also present original clock gating techniques: pre-computed clock gating. To validate these techniqu...
Conference Paper
Full-text available
Embedded systems allow application-specific optimiza- tions to improve the power/performance trade-off. In this paper, we show how application-specific hashing of the ad- dress can eliminate a large number of conflict misses in caches. We consider XOR-functions: each set index bit is computed as the XOR of a subset of the address bits. Previous wor...