Jean-Christophe Le Lann

National Institute of Advanced Technologies of Brittany · Lab-STICC

In this paper, we introduce an efficient algorithm for automating the direct transformation of a control flow graph (CFG) into a synthesizable finite-state machine with implicit datapath (FSMD). In our opinion, this transformation has not received sufficient attention: although the passage of a CFG to FSMD is mentioned in many textbooks on digital...

Contractor algebra is used to characterize a set defined as a composition of sets defined by inequalities. It mainly uses interval methods combined with constraint propagation. This algebra includes the classical operations we have for sets such as the intersection, the union and the inversion. Now, it does not include the complement operator. The...

Globalization of the IC supply chain and the ever more distributed character of hardware design flows have lead to a surge in security threats. While the focus has long been on IP theft and counterfeiting issues during manufacturing, concern about vulnerabilities at design time has been growing more prevalent in recent years. With the advent of new...

The increasing design and manufacturing costs are leading to globalize the semiconductor supply chain. However, a malicious attacker can resell a stolen Intellectual Property (IP) core, demanding methods to identify a relationship between a given IP and a potentially fraudulent copy. We propose a method to protect IP cores created with high-level s...

LiteX is a GitHub-hosted SoC builder / IP library and utilities that can be used to create SoCs and full FPGA designs. Besides being open-source and BSD licensed, its originality lies in the fact that its IP components are entirely described using Migen Python internal DSL, which simplifies its design in depth. LiteX already supports various softco...

For several years, hardware design has been undergoing a surprising revival: fueled by open source initiatives, various tools and architectures have recently emerged. This resurgence also involves new hardware description languages. Inspired by the Migen Python community, we present RubyRTL, a novel internal domain-specific language for hardware de...

LiteX [1] is a GitHub-hosted SoC builder / IP library and utilities that can be used to create SoCs and full FPGA designs. Besides being open-source and BSD licensed, its originality lies in the fact that its IP components are entirely described using Migen Python internal DSL, which simplifies its design in depth. LiteX already supports various so...

Recent advances in cloud computing have led to the advent of Business-to-Business Software as a Service (SaaS) solutions, opening new opportunities for EDA. High-Level Synthesis (HLS) in the cloud is likely to offer great opportunities to hardware design companies. However, these companies are still reluctant to make such a transition, due to the n...

This paper proposes a novel approach for the hardware virtualization of FPGA resources, based on overlay architectures. Overlays are reconfigurable architectures synthesized on top of commercial-of-the-shelf (COTS) FPGAs. They have demonstrated to improve portability, speed up reconfiguration, and promote resource abstraction hence durability. This...

Reconfigurable computing is rapidly establishing itself as a major discipline, involving the use of reconfigurable devices for computing purposes. This paper proposes the ORRes approach for a time-sharing of reconfigurable resources. We investigate the overlay architecture at the hardware layer to ensure the bitstream compatibility between heteroge...

Reconfigurable cores support post-release updates which shortens time-to-market while extending circuits’ lifespan. Reconfigurable cores can be provided as hard cores (ASIC) or soft cores (RTL). Soft reconfigurable cores outperform hard reconfigurable cores by preserving the ASIC synthesis flow, at the cost of lowering scalability but also exacerba...

The continuous proliferation of multicore architectures has placed developers under great pressure to parallelize their applications in order to take advantage of such platforms. Unfortunately, traditional low-level programming models exacerbate the difficulties of building large and complex parallel applications. Consequently, programmers are faci...

Sensor networks are now one of the key technologies for the Internet of Things (IoT). An IP-based sensor network allows a natural participation of sensor nodes to the IoT. Smart IoT systems are always constrained by real-time processing. Edge computing can be used to address this constraint. In such system, sensor nodes are often in need of more pr...

Présentation des travaux de Theotime Bollengier, sur les overlays grain-fin.

Overlays are reconfigurable architectures synthesized on commercial of the shelf (COTS) FPGAs. Overlays bring some advantages such as portability, resources abstraction, fast configuration, and can exhibit features independent from the host FPGA. We designed a fine-grained overlay implementing novel features easing the management of such architectu...

The incorporation of traditional FPGAs in datacenters is a solution brought for delivering a powerful, flexible and energy-efficient cloud computing. In this context, we propose a software/hardware framework for integrating virtualized FPGA-based hardware accelerators into traditional cloud computing systems. The virtual FPGAs are FPGA-like overlay...

Les overlays connaissent actuellement un regain d’intérêt car ces architectures offrent plusieurs avantages : disponibilité (une overlay est une IP), facilité de programmation, rapidité de configuration. Cet article présente une plateforme pour l’exploitation d’overlays comme accélérateurs matériels dans un cadre cloud. L’accent est mis sur la migr...

Loosely coupled accelerators allow an intensive “pure software program” (PSP) to share data seamlessly with ac- celerators. The method involves rewriting the source code, the hardware synthesis of the accelerated parts, and, of course, an architectural support. At algorithm design time, processing is translated into coarse grain steps. Steps group...

With the advent of multicore processor architec-tures and the existence of a huge legacy code base, the need for efficient and scalable parallelizing compilers is growing. Where multi-core processors were seen as the way forward to address the known challenges such as the memory, power and ILP wall, efficient parallelization to make use of the mult...

Improvements in system cost, size, performance, power dissipation, and design turnaround time are the key benefits offered by System-on-Chip designs. However they come at the cost of an increased complexity and long development cycles. Integrating reconfigurable cores offers a way to increase their flexibility and lifespan. However the integration...

Virtualization has been a key enabler for trading raw performances for programmability, straightforward reuse and higher abstraction in the software world. Similarly, Virtual FPGAs define intermediate fabrics, on which to implement applications regardless of the physical target. In order to make legacy applications run on up-to-date targets, only p...

Pipeline execution pattern is a recurrent execution configuration in many application domains involving stream processing such as digital signal processing and data compression. Unfortunately, low-level parallel programming models exacerbate the difficulties of expressing pipeline parallelism and require verbose restructuring of the code and comple...

Effective cache utilization is critical to performa nce in chip-multiprocessor systems (CMP). Modern CMP architectures are based on hierarchical cache topology with varying private and shared caches configurations at different levels. C ache-aware scheduling has become a great design challenge. Many scheduling strategies have b een designed to...

General-purpose shared memory multicore architectures are becoming widely available. They are likely to stand as attractive alternatives to more specialized processing architectures such as FPGA and DSP-based platforms to perform real-time digital signal processing. In this paper, we show how we can ease parallelism expression on shared memory mult...

The continuous proliferation of multicore architectures has placed developers under great pressure to parallelize their applications in order to take advantage of such platforms. Unfortunately, traditional low-level programming models exacerbate the difficulties of building large and complex parallel applications. Consequently, programmers are faci...

Cabled sea floor observatories are used to study the oceans. Not only the amount of data they generate is too large to be treated manually, but also a lot of irrelevant data degrades the treatment efficiency. Treating the acquired data at the source reduces the amount of data. But this leads to the design of complex sensors mixing data acquisition...

The need for higher level models during system design has resulted in many different Electronic System Level (ESL) formalisms that seldom succeeded in the past in the quest for efficient top-down design methodologies. In this paper, we propose a new working toolchain starting from UML specifi-cations coupled to an industrial-level system-level synt...

A chain of three state-of-the-art tools is demonstrated to generate efficient code for Multi-Processors System-on-Chips (MPSoCs) from a high-level dataflow language. The experimental platform is based on a 5-core Texas Instruments OMAP4 heterogeneous MPSoC running an image processing application.

The continuous proliferation of multicore architectures has placed developers under great pressure to parallelize their applications accordingly with what such platforms can offer. Unfortunately, traditional low-level programming models exacerbate the difficulties of building large and complex parallel applications. High-level parallel programming...

JOG est un robot mobile indoor dédié à l'enseignement des systèmes embarqués à base de processeur ARM, du système d'exploitation Linux et d'une machine virtuelle Java. JOG permet d'aborder le développement d'un système embarqué complet avec un langage de haut niveau, Java, sans pour autant faire abstraction des aspects matériels du système. Une API...

Today, developments of Real Time Embedded Systems have to face new challenges. On the one hand, Time-To-Market constraints require a reliable development process allowing quick design space exploration. On the other hand, rapidly developing technology, as stated by Moore’s law, requires techniques to handle the resulting productivity gap. In a prev...

Performance improvement on heterogeneous reconfigurable architectures depends on application analysis for parallel execution. This paper describes a performance analysis methodology for video encoding applications to estimate the expected performance of parallel execution on reconfigurable architectures. We formulate the performance estimation of a...

The Model Driven Architecture is a promising approach aiming to fill the productivity gap due to the increasing technology and time to market pressure. In the field of real time embedded systems, this approach requires the use of well-adapted formalisms in a reliable process that guarantees the quality of the products. MARTE, the new standardized U...

The invention relates to a method for decoding elements coded according to an arithmetic coding method such as CABAC. The method decodes at least a part of the binary stream into a set of elements on the basis of first and second decoding parameters CodlOffseto and CodlRange, the set of elements comprising a prefix (P2) composed of n first elements...

Morpheus promotes the transparent use of heterogeneous reconfigurable resources in system on chip. Given the variety of reconfigurable architectures and low level specification languages, it is necessary to use a robust methodology to isolate the application description languages from the possible architectural targets. The WP2 consortium has adopt...

This paper presents an integrated programming toolset for application implementation on an heterogeneous reconfigurable architecture. The objectives of the toolset are to optimize the application implementation productivity and to enable the dynamic reconfiguration on reconfigurable units of the target architecture. The proposed solution is based o...

System design based on the so-called "synchronous hypothesis" consists of abstracting non-functional implementation details of a system and lets one benefit from a focused reasoning on the logics behind the instants at which system functionalities should be secured, providing ease to generating synchronous circuits and verifying their functionaliti...

In previous work in behavioral high-level synthesis (HLS), data-flow and control-flow dominated descriptions are treated separately. A result of such a separation is that efficient techniques have been developed for the HLS of data-flow dominated behavioral descriptions. However, HLS of control-flow dominated descriptions still lags behind. To clos...

: In this report we present a methodology for designing complex hardware systems. This methodology is based on the synchronous data flow language Signal which offers a formal framework to build executable specifications of hardware components. All design steps (i.e. refinements, verification, simulation, HDL generation, ...) are based on this uniqu...

Loosely coupled accelerators allow an intensive "pure software program" (PSP) to share data seamlessly with ac-celerators. The method involves rewriting the source code, the hardware synthesis of the accelerated parts, and, of course, an architectural support. At algorithm design time, processing is translated into coarse grain steps. Steps group a...