Jagannath Samanta

Haldia Institute of Technology | Haldia · Department of Electronics and Communication Engineering

Recently, there have been continuous rising interests of multi-bit error correction codes (ECCs) for protecting memory cells from soft errors which may also enhance the reliability of memory systems. The single error correction and double error detection (SEC-DED) codes are generally employed in many high-speed memory systems. In this paper, Hsiao-...

Single error correction (SEC) codes have been employed to protect the data bits as well as control bits in wireless sensor networks (WSNs) for Internet of Things (IoT) applications. In these systems, soft error typically single event upset (SEU) has been occurred. A low delay and power efficient error correcting codes are desirable in most of the w...

Frequently, soft errors occur due to striking of radioactive particles in memory cells which reduce the reliability of memory systems. Generally, single error correction-double error detection (SEC-DED) codes are employed to detect and correct the soft errors in semiconductor memory systems. In this paper, a new optimization algorithm is proposed b...

Mostly random and adjacent error correcting codes are used to protect stored data in SRAMs against multiple bit upsets (MBUs). These MBUs caused by radiation are an important issue related to the reliability of static random access memories (SRAMs). As a result, multiple adjacent bits of a memory are distorted and valuable information is lost. To m...

Multiple cell upsets (MCUs) caused by radiation is an important issue related to the reliability of embedded static random access memories (SRAMs). Multiple random and adjacent error correcting codes have been extensively employed for several years to protect stored data in SRAMs against MCUs. A compact and fast error correcting codec is desirable...

Multiple cell upsets (MCUs) caused by radiation is an important issue related to the reliability of embedded static random access memories (SRAMs). Multiple random and adjacent error correcting codes have been extensively employed for several years to protect stored data in SRAMs against MCUs. A compact and fast error correcting codec is desirable...

This comment points out the mistakes of one figure, one flowchart, and six tables in reference [1]. Here we have provided the corrected version of figure, flowchart, and tables.

Memory contents are usually corrupted due to soft errors caused by external radiation and hence the reliability of memory systems is reduced. In order to enhance the reliability of memory systems, error correcting codes (ECC) are widely used to detect and correct errors. Single bit error correcting with double bits errors detecting codes are genera...

Generally in digital communication systems and storage mediums, Reed–Solomon (RS) codes are employed to detect and correct errors. RS code is a promising code for Ultra Wide Band (UWB) which is ideally suitable for wireless application. Design of compact, high-speed and low-power RS(23, 17) code is challenging for today’s wireless communication sys...

Cellular automata is already employed by several researchers for designing bit and byte error detecting and correcting codes. Cellular automata based VLSI design is attractive because of its modular, regular and cascadable construction. Reed-Solomon codes are popularly used to detect and correct burst and as well as random errors in different commu...

Finite field arithmetics are often used in linear block codes such as BCH and Reed–Solomon codes and also in cryptographic algorithms. Finite field multipliers play an important role and consume a significant amount of area in VLSI design. This paper presents an improved generalized Karatsuba multiplier. Optimization of the Karatsuba multiplication...

Different adder circuits are elementary blocks in many contemporary integrated circuits, which are not only employed to perform addition operations, but also other arithmetic operations such as subtraction, multiplication and division. Full adder is the basic building block of any adder circuit. Area, speed and power are the three main design metri...

Reed–Solomon codes are commonly used to detect and correct errors in digital data during transmission and storage. In this paper, a new optimization algorithm has been proposed which is very simple and efficient for reducing the complexity of the Galois field constant multipliers in terms of XOR2 gates, and hence, the area overhead of RS(32, 28) en...

Design of high speed, low power and area-efficient logic circuits are the most challenging areas of research in VLSI and embedded system design. Adders are the main building blocks in microprocessor as well as DSP processor. Most adders come with the problem of carry propagation delay. To overcome such a problem Carry Select Adder is used as the fu...

XOR & AND gates are most important basic building blocks of any VLSI applications. These gates can be implemented in different architectures by using different circuit designs techniques. This paper evaluates and compares the performance of various design techniques of XOR-AND gates. The performances of these techniques have been evaluated by Tanne...

A carry look-ahead adder improves speed by reducing the amount of time required to resolve carry bits. It is widely used in any electronic computational devices. In this paper a 4 bit & 8 bit CLA has been implemented using different static and dynamic logic styles such as Standard CMOS, DCVS Pseudo NMOS, PTL & Domino logic style. The performance of...

Reed-Solomon Codes are popularly used for error correction in many applications like storage devices (CD, DVD), wireless communications, high speed modems and satellite communications. In this paper, a modified scheme for programmable generator polynomial based Reed-Solomon encoder and decoder has been proposed. The works reported in this paper cor...

This paper presents an I-V model for estimating the drain current of a sub-90nm MOSFET in the linear and saturation regions. The proposed model employs the dependencies of drain current on channel width and the gate voltage. It is the modification of nth-power law model introduced by Sakurai and Newton. Our model provides more accurate relationship...

In this paper, we have modified a low-voltage, low- power VT (Threshold Voltage) extractor circuit, and by doing this we have obtained results with greater accuracy. At the same time, the output generated from this circuit is found to be robust enough against supply voltage variations. This scheme is based on the most popular extraction algorithm w...

Adders are key components in digital design, performing not only addition operations, but also many other functions such as subtraction, multiplication and division. Adders of various bit widths are frequently required in Very Large-Scale Integrated circuits (VLSI) from processors to Application Specific Integrated Circuits (ASICs). In this work, w...

Propagation delay is one of the important issues for designing and synthesizing any VLSI circuits. In this paper, a simple and accurate delay model has been developed for Ultra Deep Sub-Micron (UDSM) CMOS inverter based on nth power law of MOSFET model when the channel length is in the order of less than or equal to 90nm. Modified model is also app...

Short-channel effects play a major role for MOS scaling of gate length down and especially below 0.1μm or even less. In this paper, the detail review of different secondary effects and their solutions for delay & power estimation which are proposed by various researchers in the past decade are presented briefly. Different effects like Gate Direct T...

Delay and power are two major issues in design and synthesis of VLSI circuits which depends on different design parameters. In this paper, the relative study of propagation delay and power consumption of UDSM CMOS inverter is found considering the channel length below 100nm. The simulation results are taken for different technology (32nm, 45nm, 65n...

196  Abstract— A pseudo-orthogonal prime sequence code and a modified prime sequence code using the elements of Galoi's Field (GF) for a particular prime number have been developed. Bit-error rate performances using Gaussian approximation technique have been made. The capacities of the prime sequence codes are determined. Detailed simulation resul...

Due to increase in MOS scaling, frequency and bandwidth of high performance CMOS VLSI circuits, on-chip consumed power is enhanced. It creates an important role in both switching and dc power dissipation. This dissipated power is usually rehabilitated into degenerated heat, affecting the performance and consistency of a chip. In this paper we contr...

In this paper, we have developed a simple and accurate delay model for any Ultra Deep Sub-micron (UDSM) CMOS inverter, NAND2 & NOR2 based on nth power law of MOSFET model when the channel length is of the order of less than or equal to 90nm. We have taken all the parameters from BSIM.4.6.1 manual. This work derives analytical expression for the del...