Jacek Bieganowski

• PhD
• Professor (Assistant) at University of Zielona Góra

Methods for reducing power consumption in circuits of finite state machines (FSMs) are discussed in this review. The review outlines the main approaches to solving this problem that have been developed over the last 40 years. The main sources of power dissipation in CMOS circuits are shown; the static and dynamic components of this phenomenon are a...

The Chapter is devoted to hardware reduction targeting the normal LCS-based Moore FSMs. Firstly, the optimization methods are proposed for the base model of NFSM. They are based on the executing either optimal state assignment or transformation of state codes. Two different models are proposed for the case of code transformation. They depend on the...

The Chapter deals with optimization of logic circuits of hybrid FPGA-based Mealy FSMs. First of all, the models with two state registers are discussed. This approach allows removal of direct dependence among logical conditions and output functions of Mealy FSM. Next, the proposed design methods are presented. Some improvements are proposed for furt...

The Chapter is devoted to hardware reduction targeting the extended LCS-based Moore FSMs. Firstly, the design method is proposed for the base model of XFSM. Next, the methods are proposed targeting the hardware reduction in the circuits based on this model. They are based on the executing either optimal state assignment or transformation of state c...

The Chapter is devoted to hardware reduction targeting the elementary LCS-based Moore FSMs. Firstly, the optimization methods are proposed for the base model of EFSM. They are based on the executing either optimal state assignment or transformation of state codes. Two different models are proposed for the case of code transformation. They depend on...

The Chapter is devoted to the using linear chains in FSMs. The counter-based microprogram control units are discussed, as well as known PLA-based structures of Moore FSMs. Then there are discussed methods of optimal state assignment and transformation of state codes into codes of classes of pseudoequivalent states (PES). Next there are introduced d...

The Chapter provides some basic information. Firstly, the language of GSA is introduced. Next, the connections are shown with GSAs and state transition graphs of both Mealy and Moore FSMs. Classical principles of FSM logic synthesis are discussed. The basic features of FPGA are analyzed. It is shown that embedded memory blocks allow implementing sy...

The Chapter is devoted to the problems of hardware reducing for FPGA-based logic circuits of Moore FSMs. The design methods are proposed based on using more than one source of codes of classes of pseudoequivalent states (PES). Two structural diagrams and design methods are proposed for Moore FSM based on transformation of objects. The first method...

This book discusses Moore finite state machines (FSMs) implemented with field programmable gate arrays (FPGAs) including look-up table (LUT) elements and embedded memory blocks (EMBs). To minimize the number of LUTs in FSM logic circuits, the authors propose replacing a state register with a state counter. They also put forward an approach allowing...

A method of hardware reduction is proposed for logic circuits of Moore FSMs implemented with FPGAs. The method is based on the idea of code sharing. The main difference from already known methods is that the counter increases its content during conditional and unconditional transitions. An example of application of proposed method is given.

The chapter is devoted to CMCU optimization, based on the modification of the microinstruction format. Proposed modifications are intended to eliminate code transformers from the CMCU and reduce the hardware amount of circuits used in the FSM for the microinstruction addressing, as compared with the CMCU basic structure. The reduction of the hardwa...

Reduction in the number of LUT elements for control units with code sharing Two methods are proposed targeted at reduction in the number of look-up table elements in logic circuits of compositional microprogram control units (CMCUs) with code sharing. The methods assume the application of field-programmable gate arrays for the implementation of the...

The paper presents a synthesis method that allows reduction of the number of look-up table (LUT) elements in logic circuits of compositional microprogram control units (CMCU) with code sharing. The method is mainly targeted for field-programmable gate arrays (FPGA) with embedded-memory blocks (EMB) but can be also used in case of Complex Programmab...

The paper presents new research results of synthesis of compositional microprogram control unit with extended microinstruction format. The method is addressed for programmable logic devices such as CPLD and FPGA and it is oriented on reduction of hardware amount of CMCU addressing circuit. The reduction is reached due to decrease of the number of t...

The method that considers optimization of the amount of PAL macrocells in the circuit of compositional microprogram control unit is proposed. The method is based on the introduction of additional microinstructions codes of the classes of pseudoequivalent operational linear chains. The proposed method is based on usage of the natural redundancy of e...

The method of optimization of the hardware amount in addressing circuit of compositional microprogram control unit is proposed. Method is based on expansion of the microinstruction format by the field with code of the class of pseudoequivalent operational linear chains. Minimization is reached due to decreasing of the number of terms in system of B...

A new method of detecting deadlocks and traps in Petri nets is presented. Deadlocks and traps in Petri nets can be represented by the roots of special equations in CNF form. Such equations can be solved by using the search tree algorithm proposed by Thelen. In order to decrease the tree size and to accelerate the computations, some heuristics for T...

Streszczenie: W artykule przedstawiona została metoda syntezy umożliwiająca zmniejszenie liczby tablic LUT potrzebnych do realizacji układu mikroprogramowanego z współdzieleniem kodów. Metoda jest przeznaczona dla układów FPGA z osadzonymi blokami pamięci. Część kombinacyjna układu mikroprogramowanego jest realizowana z użyciem tablic LUT, natomias...

Thelen's algorithm is an efficient method for generation of the prime implicants of a Boolean function represented in CNF. In the paper new heuristics are presented, allowing to accelerate the algorithm. Experimental analysis of their effects is performed.

The method of optimization of amount of PAL macrocells in the circuit of compositional microprogram control units proposed. The method is based on introducing of additional microinstructions with codes of the classes of pseudoequivalent operational linear chains. The proposed method is based on usage of natural redundancy of embedded memory blocks...