Isuru Nawinne

Isuru Nawinne
UNSW Sydney | UNSW · School of Computer Science and Engineering

PhD in Computer Science & Engineering

About

12
Publications
1,396
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41
Citations

Publications

Publications (12)
Preprint
Recently, researchers in the field of interactive computer gaming have introduced two technologies that can be integrated into game engines to provide a better user experience: dynamic difficulty adjustment (DDA); affect-based difficulty adjustment (Affect-DA). DDAsystems monitor the performance of the user to dynamically adjust the difficulty leve...
Article
Full-text available
Recently, researchers in the area of biosensor based human emotion recognition have used different types of machine learning models for recognizing human emotions. However, most of them still lack the ability to recognize human emotions with higher classification accuracy incorporating a limited number of bio-sensors. In the domain of machine learn...
Preprint
Full-text available
Sleep apnea is a breathing disorder where a person repeatedly stops breathing in sleep. Early detection is crucial for infants because it might bring long term adversities. The existing accurate detection mechanism (pulse oximetry) is a skin contact measurement. The existing non-contact mechanisms (acoustics, video processing) are not accurate enou...
Article
Caches are used to improve memory access time and energy consumption. The cache configuration which enables the best performance often differs between applications due to diverse memory access patterns. The authors present a new concept, called switchable cache, where multiple cache configurations exist on chip, leveraging the abundant transistors...
Article
Multiprocessor systems make use of multilevel cache hierarchies to improve overall memory access speed. Embedded systems typically use configurable processors, where the caches in the system can be customized for a given application or a set of applications. Finding the optimal or a near-optimal set size, block size, and associativity of each of th...
Conference Paper
Multi-level caches are widely used to improve the memory access speed of multiprocessor systems. Deciding on a suitable set of cache memories for an application specific embedded system's memory hierarchy is a tedious problem, particularly in the case of MPSoCs. To accurately determine the number of hits and misses for all the configurations in the...
Conference Paper
Caching is the most widely used solution to improve the memory access speed of a processor. Behaviour of a cache memory is characterized by several parameters such as the set size, associativity, block size and replacement policy which compose the configuration of the cache. Cache hits and misses encountered by an application are decided by the con...
Conference Paper
Mapping tasks to cores in an Multiprocessor System-on-Chip (MPSoC) to meet constraints is widely investigated. Thus far the data flow graphs used for binding have been limited to acyclic graphs or have been single rate. In this paper we generalize the approach by allowing DFGs to be cyclic and multi rate. We further improve energy consumption by se...
Conference Paper
Full-text available
Processing data received as a stream is a task commonly performed by modern embedded devices, in a wide range of applications such as multimedia (encoding/decoding/ playing media), networking (switching and routing), digital security, scientific data processing, etc. Such processing normally tends to be calculation intensive and therefore requiring...

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