Isabel C. Teixeira

Ultra-low-power strategies have a huge importance in today's integrated circuits designed for internet of everything (IoE) applications, as all portable devices quest for the never-ending battery life. Dynamic voltage and frequency scaling techniques can be rewarding, and the drastic power savings obtained in subthreshold voltage operation makes th...

Human-Computer Interaction (HCI) applications need reliable hardware and the development of today’s sensors and cyber-physical systems for HCI applications is critical. Moreover, such hardware is becoming more and more self-powered, and mobile devices are today important devices for HCI applications. While battery-operated devices quest for the nev...

Data acquisition hardware of ITER diagnostics if located in the port cells of the tokamak, as an example, will be irradiated with neutrons during the fusion reactor operation. Due to this reason the majority of the hardware containing Field Programmable Gate Arrays (FPGA) will be placed after the ITER bio-shield, such as the cubicles instrumentatio...

A presente invenção refere-se a um sistema para optimizar de forma dinâmica a operação ao longo da vida de circuitos integrados digitais síncronos, permitindo que os circuitos sejam optimizados de acordo com duas necessidades possíveis: (i) restringir a dissipação de potência, reduzindo a tensão de alimentação para o valor mínimo que impede a ocorr...

In current CMOS nanometer technologies, aging effects may appear after relatively short operating times, compared to the expected lifetime of circuits. Therefore, there is an increasing need for on-chip aging monitoring, especially in high-performance, safety critical systems. This paper presents a programmable aging sensor that can be embedded in...

The implementation of complex, high-performance digital functionality in nanometer CMOS technologies faces significant design and test challenges related to the increased susceptibility to process variations and environmental or operation-dependent disturbances. This paper proposes the application of unified semi-empirical propagation delay variati...

Electronic design of high-performance digital systems in nano-scale CMOS technologies under Process, power supply Voltage, Temperature and Aging (PVTA) variations is a challenging task. Such variations induce abnormal timing delays leading to systems errors, harmful in safety-critical applications. Performance Failure Prediction (PFP), instead of e...

The ITER Fast Plant System Controllers (FPSC) are based on embedded technologies and will be devoted to both data acquisition tasks (sampling rates >1 kSPS) and control purposes in closed-control loops whose cycle times are below 1 ms. Fast Controllers will be dedicated industrial controllers with the ability to: i) supervise other fast and/or slow...

The purpose of this paper is to demonstrate that adequate delay modeling of Field Programmable Gate Array (FPGA) "elements," together with time borrowing techniques, can be effectively used to define the lowest power supply voltage (VDD) value that allows correct functionality to be assured, within a specified system performance. One of the key tec...

There is a continuously increasing demand for lower power consumption and higher operating frequencies in digital systems. In addition, external or operation-induced disturbances may significantly affect circuit functionality or performance. This paper analyzes the effect of power supply disturbances on the propagation delays of digital circuits im...

In the framework of the Clear-PEM project for the construction of a high-resolution scanner for breast cancer imaging, a very compact and dense frontend electronics system has been developed for readout of multi-pixel S8550 Hamamatsu APDs. The frontend electronics are instrumented with a mixed-signal Application-Specific Integrated Circuit (ASIC),...

The purpose of this paper is to present recent developments in the off-detector electronics of a PET (Positron Emission Tomography) system for mammography imaging. In particular, problems and solutions associated with the integration of its Data Acquisition Electronics are targeted. Synchronism is a critical issue in the DAE system. A resynchroniza...

A Portuguese consortium has developed a PET scanner dedicated to breast cancer detection (Clear-PEM within the framework of the international Crystal Clear Collaboration at CERN. In the construction of this scanner several challenges have been addressed, from the design of the photon's detector, front-end electronics and data acquisition systems up...

Complex electronic systems for safety or mission-critical applications (automotive, space) must operate for many years in harsh environments. Reliability issues are worsening with device scaling down, while performance and quality requirements are increasing. One of the key reliability issues is to monitor long-term performance degradation due to a...

The implementation of complex functionality in low-power (LP) nano-CMOS technologies must be carried out in the presence of enhanced susceptibility to PVT (Process, power supply Voltage and Temperature) variations. VT variations are environmental or operation-dependent parametric disturbances. Power constraints (in normal and test mode) are critica...

The implementation of complex, high-performance functionalities in low-power nano-CMOS technologies faces significant design and test challenges related to the increased susceptibility to environmental or operation-dependent disturbances, process variations or emerging defect types. This paper describes the application of semi-empirical propagation...

Obtaining images with high resolution and contrast from short exams is crucial for the viability of Positron Emission Mammography as an early breast cancer detection technique. The Clear-PEM detector is a Positron Emission Mammography scanner, developed by the Portuguese Consortium in the framework of the Crystal Clear Collaboration at CERN, based...

This article proposes a new methodology for enhancing SoC signal integrity without degrading performance in the presence of power-ground voltage transients. The underlying principle is the dynamic adaptation of the clock duty cycle to propagation delay variation along disturbed logic paths. This methodology makes digital circuits more robust to pow...

Dans IET Computers & Digital Techniques, serie 5, vol. 1, p443

The energy resolution of the barrel part of the CMS Electromagnetic Calorimeter has been studied using electrons of 20 to 250 GeV in a test beam. The incident electron's energy was reconstructed by summing the energy measured in arrays of 3x3 or 5x5 channels. There was no significant amount of correlated noise observed within these arrays. For elec...

As IC technology scales down, power supply instability may dramatically contribute to signal integrity loss. In this paper, the authors propose a new methodology to enhance circuit tolerance to power-supply voltage (VDD1) local variations, without degrading its performance. The underlying idea is to add additional tolerance to the edge trigger of t...

New product development using nanometer semiconductor technologies require high-quality BIST solutions able to uncover dynamic faults. Most existing solutions rely on test-per-scan BIST, for high fault coverage. However, reconfiguration, in test mode, may significantly modify delays in signal paths, thus reducing the degree of confidence of dynamic...

The computational effort associated with fault simulation (FS) processes in digital systems can become overwhelming, due to circuit complexity, test pattern size or fault list size. The same applies when safety properties (such as fault tolerance or fail-safe) need to be verified in a new product development, in the design environment. If a bridgin...

Product development economics and specs drive the need for on chip embedded test functionality. However, optimal partitioning of test functionality between a tester and a SOC is a non-trivial task, which must be solved during the system analysis phase. Hence, at system level, a trade-off analysis must be performed, in order to evaluate the costs an...

This paper presents a methodology and tool support for the development of distributed real-time object-oriented systems, focusing on industrial automation applications. At system level, two different kinds of classes/objects are recognized: (i) application domain objects, which map directly to concepts and components of the problem domain, and (ii)...

Product development economics and specs drive the need for on chip embedded test functionality. However, optimal partitioning of test functionality between a tester and a SOC is a non-trivial task, which must be solved during the system analysis phase. Hence, at system level, a trade-off analysis must be performed, in order to evaluate the costs an...

The purpose of this paper is to introduce a new RTL testability metric, IFMB, that evaluates the exercise of Implicit Functionality (IF) of operators and Multiple Branch (AM) coverage of conditional constructs. Although physical Defect Coverage (DC) strongly depends on the logic structure, thus preventing accurate DC estimation, RTL fault models ca...

An abstract is not available.

The purpose of this paper is to present a design methodology that complements existing methodologies by addressing the upper and the lower extremes of the design flow. The aim of the methodology is to increase design and product quality. At system level, emphasis is given to architecture generation, reconfiguration and quality assessment. Quality m...

The paper presents a novel approach to the automatic identification of objects/classes from a system specification. The methodology is aimed at the development of distributed real time systems (DRTS), especially those conceived for industrial automation applications. UML is used as the modeling language in conjunction with an extended version of tr...

The purpose of this paper is to present a design methodology that complements existing methodologies by addressing the upper and the lower extremes of the design flow. The aim of the methodology is to increase design and product quality. At system level, emphasis is given to architecture generation, reconfiguration and quality assessment. Quality m...

The purpose of this paper is to show that functionality distribution among embedded objects of a system architecture critically influences the quality of the resulting architecture. It is shown that gains can be achieved when functionality distribution is guided by optimization criteria, using an automatically generated centralized processing archi...

The purpose of this paper is to present a novel methodology for assessing the quality of architecture solutions of hw/sw systems, with particular emphasis on testability. Criteria and metrics for quality assessment are proposed and used to assist the design team in selecting a ‘best-fitted’ architecture that satisfies not only functional requiremen...

The purpose of this paper is to present an environment that allows the reliable, in-time system specification and design of complex hardware/software (HW/SW) systems. The Object Oriented (OO) paradigm underlies models, methodologies, languages and tools. Three different tools are available, SIMOO, a CASE tool is used during analysis and specificati...

The purpose of this paper is to demonstrate the usefulness of a recently proposed Object-Oriented (OO) based methodology and tools (SysObj and Test-Adder) when applied in the design of testable hardware modules (eventually used as embedded cores in SOCs). A public domain processor (PIG) is the vehicle for such assessment. A boundary scan soft wrapp...

Manufacturing test of microelectronics integrated circuits and products based thereon has now become one of the most challenging problems facing the semiconductor industry. There are several fundamental challenges such as potential yield loss due to ...

The purpose of this paper is to present an environment that allows the reliable. in-time system specification and design of complex hardware/software (hw/sw) systems. The Object Oriented (OO) paradigm underlies models, methodologies, languages and tools. Three different tools are available. SIMOO, a CASE tool is used during analysis and specificati...

The purpose of this paper is to present a novel methodology for the estimation of VLSI products defect level, or reject rates, in the IC design environment. A new defect-oriented (DO) fault extraction and stratified sampling technique, implemented in an extraction tool, lobs, is used with a novel DO fault simulation tool, veriDOFS, which uses a com...

The purpose of this paper is to present a methodology for modeling, at system level, complex real-time hw/sw systems. The methodology makes use of an object-oriented modeling technique. A method is proposed to integrate the time dimension at system level specification. The method adapts some concepts of UML. The quality of the architectural solutio...

The purpose of this paper is to present a methodology for circuit and realistic fault extraction, and its implementation in a new tool, lobs, to be included in a virtual test environment, DOTLab. Digital, analog and mixed signal ICs, implemented in CMOS, bipolar or BiCMOS technologies are handled, both in Manhattan and 45 degrees geometries. Higher...

High quality analog and mixed signal integrated circuits (ICs) require high quality testing. It is shown that test preparation, and test quality improvement of analog building blocks must be layout driven. For this, an IC defects-based analysis is used to study the impact of catastrophic faults on basic CMOS analog blocks. The impact on circuit beh...

A new methodology for test preparation, at gate level, is introduced. Realistic bridging faults between logical nodes are used as a fault model. The methodology requires logic circuit extraction, from the transistor circuit netlist: hence, a new logic extractor for static CMOS designs, tabloid, is presented. Preliminary results on logic extraction,...

The basic purpose of this paper is to present a physical analysis of the transient behaviour of CMOS circuits. A chain of inverters is used as a vehicle for deriving general conclusions on the intimate physics of the switching process in CMOS digital networks. The analysis emphasizes the role of the dynamic threshold voltages, which definite the in...

Microelectronic technologies made possible the implementation of solid state based metering systems. In this paper, an ASIC design that implements all but the analog part of a watt-hour meter is described. This ASIC designed with the APBB technology is intended to be used in conjunction with the Ferraris power meter in a hybrid telecounting system...

Integrated circuits (ICs) need to be designed for testability. The purpose of this paper is to present a strategy for testability enhancement, at the lower levels of the design, which is supported in hardware refinement and software improvement. Main areas of low-cost software improvement, for test preparation, are identified as logic extraction, t...

The purpose of this paper is to describe key aspects of the integration and test of the Data Acquisition Electronics (DAE) in the PEM (Positron Emission Mammography) system. The main aspects highlighted are the methodology and strategies followed to test and validate the functionality and performance of the complete physical system. Test procedures...

Performance tests of some aspects of the CMS ECAL were carried out on modules of the "barrel" sub-system in 2002 and 2003. A brief test with high energy electron beams was made in late 2003 to validate prototypes of the new Very Front End electronics. The final versions of the monitoring and cooling systems, and of the high and low voltage regulati...