Ionut Radu

• PhD
• Technologist, Microelectronics at Soitec

Silicon Carbide (SiC) Power Devices have emerged as a breakthrough technology for a wide range of applications in the frame of high-power electronics, notably in the 600 to 3,300V. The last decades have shown a continuous and impressive improvement in both 4H-SiC wafer size and quality. Nevertheless, the availability of such wafers remains a challe...

In this work, we report the concept and experimentally demonstrate the first tunable ferroelectric (Fe) junctionless (JL) transistor (Fe-JLFET), capable of emulating the functionality of biological tri-partite synapses, which is an artificial three-terminal synapse with unique back gate high tuning of the post-synaptic current (PSC). Our device con...

Silicon Carbide (SiC) Power Devices have emerged as a breakthrough technology for a wide range of applications in the frame of high power electronics. Despite the continuously improving quality and supply of 4H-SiC substrates, the availability of such wafers is still insufficient. An advantageous opportunity is offered by the Smart CutTM technology...

Large‐Diameter III–V Materials on Si Substrates Compared to silicon substrates, III–V materials (GaAs, InP, ect) are limited to small diameters. In article number 2100543, Bruno Ghyselen and co‐workers propose to extend the diameter range of the III–V materials by combining the Smart Cut process (a wafer bonding and layer transfer technique, Smart...

Compared to silicon substrates, III-V materials based on GaAs and/or InP are generally limited to small diameters, up to 150 mm for GaAs and 100 mm for InP, even though bulk wafers of 150 mm diameter have already been sampled. In this paper, a new technology is proposed to extend the diameter of these materials by combining the Smart CutTM technolo...

We report record performances in Top-tier nMOSFETs fabricated by 3D sequential integration, as well as junction optimization guidelines to further optimize the performances within a maximum thermal budget of 500°C. We reached I ON =870µA/µm at I OFF =100nA/µm V DD =1V together with A VT =1.35mV.µm and a decent PBTI lifetime. Moreover, a first gener...

RF losses and nonlinearities of the commercially available Soitec radio frequency enhanced signal integrity (RFeSI) high-resistivity silicon-on-insulator substrates are investigated through investigation of 50-Ω coplanar waveguide lines manufactured on them. It is shown that the losses of the RFeSI substrates are very small. They have a temperature...

High-resistivity (HR) silicon-on-insulator (SOI) substrates provide low substrate loss, so planar spiral inductors integrated on them presenting higher quality factor (Q) than those on traditional Si substrates. However, the parasitic surface conduction (PSC) effect in the SOI substrate constitutes a conductive layer underneath the buried oxide lay...

In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs) wafer on insulator (InGaAs-OI) substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB) and Smart Cut™ technology. Three key process steps of the integration we...

Trap rich silicon-on-insulator (TR-SOI) substrates have been widely adopted for high performance RFICs in cellular front-ends over the past few years. With the more stringent loss and harmonic requirements for 4G and even 5G networks, TR-SOI substrate's quality has been improved continuously since its introduction. Two representative types of comme...

In this work we demonstrate for the first time 300 mm InGaAs on Insulator (InGaAs-OI) substrates. A 30 nm thick InGaAs layer was successfully transferred using low temperature Direct Wafer Bonding (DWB) and the Smart Cut TM technology. The epitaxial growing process has been optimized to reduce the surface roughness of the InGaAs film at around 1.5...

Wafer level stacking of single crystal films enables 3D monolithic integration of electronic devices. The monolithic stacking technology based on Smart CutTM enables front end integration of large variety of devices with nanometer alignment capability; therefore it provides more degree of freedom for the designers and integration for high density a...

The invention provides methods and structures for fabricating a semiconductor structure and particularly for forming a semiconductor structure with improved planarity for achieving a bonded semiconductor structure comprising a processed semiconductor structure and a number of bonded semiconductor layers. Methods for forming semiconductor structures...

A method for curing defects associated with the implantation of atomic species into a semiconductor layer transferred onto a receiver substrate, wherein the semiconductor layer is thermally insulated from the receiver substrate by a low thermal conductivity layer having thermal conductivity that is lower than that of the transferred semiconductor l...

A simple model describing the hydrophilic adhesion between solid surfaces, with low roughness is proposed to explain both the influence of the interface roughness and quantity of water present at the interface on the work of adhesion and work of separation. The observed hysteresis between adhesion and separation is explained by the evolving distrib...

The influence of the dynamics of the direct wafer bonding process on the curvature of the final wafer stack is investigated. An analytical model for the final curvature of the bonded wafers is developed, as a function of the different load components acting during the bonding front propagation, using thin plate theory and considering a strain disco...

Methods of bonding together semiconductor structures include annealing metal of a feature on a semiconductor structure prior to directly bonding the feature to a metal feature of another semiconductor structure to form a bonded metal structure, and annealing the bonded metal structure after the bonding process. The thermal budget of the first annea...

A method for producing a structure having an ultra thin buried oxide (UTBOX) layer by assembling a donor substrate with a receiver substrate wherein at least one of the substrates includes an insulating layer having a thickness of less than 50 nm that faces the other substrate, conducting a first heat treatment for reinforcing the assembly between...

Physical and electrical characterization of thin doped silicon films is performed at different stage of low temperature layer transfer process. Spreading Resistance Profiling (SRP), Hall effect combined with Van der Pauw technique and standard I(V) measurements of p-n junctions are performed. Dopant deactivation above 95% is observed after hydrogen...

3D integration aims at providing highly integrated systems by vertically stacking and connecting various materials, technologies, and functional components together. We will review the different approaches, using direct bonding, developed to address 3D devices manufacturing challenges.

Low temperature 3D wafer stacking for very high density device integration is achieved using the Smart CutTM technology and solid phase re-crystallization. Thin silicon PN bilayers of high quality are transferred onto new handle substrate without exceeding 500°C. The current-voltage characteristics of the intrinsic PN diode are significantly improv...

Methods of bonding together semiconductor structures include annealing a first metal feature on a first semiconductor structure, bonding the first metal feature to a second metal feature of a second semiconductor structure to form a bonded metal structure that comprises the first metal feature and the second metal feature, and annealing the bonded...

During direct bonding, a thin gas film is trapped in-between the two wafers, leading to an interactive fluid/structure dynamics. A model of bonding dynamics is formulated using the plate approximation, Reynolds equation, and adhesion forces as the boundary condition at the bonding front. The transient equation is solved numerically in a one dimensi...

Methods of forming bonded semiconductor structures include temporarily, directly bonding together semiconductor structures, thinning at least one of the semiconductor structures, and subsequently permanently bonding the thinned semiconductor structure to another semiconductor structure. The temporary, direct bond may be established without the use...

The effect of several surface treatments such as chemical-mechanical polishing or plasma activation applied to deposited silicon oxide layer surfaces prior to direct bonding has been investigated. It is shown that these treatments have a direct impact on surface and near subsurface OH bond densities which greatly participate in bonding energy chang...

Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor struct...

The wafer stacking technology for 3D integration requires high quality bonding interfaces with uniform bonding films. Two wafer level stacking technologies - Smart Stacking™ and Smart Cut™ - are developed to address the manufacturing challenges for improved process cost efficiency.

While significant research effort on various planar approaches, the 3D vertical IC stacking is undoubtedly gaining increasing momentum as a leading contender in the challenge to meet performance, cost, and size demands through this decade and beyond. The Smart Cut (TM) technology allowing the stack of very thin layers with direct bonding is one of...

The effect of several treatments such as CMP or plasma activation applied to deposited silicon oxide layer surfaces prior to direct bonding has been investigated. It is shown that these treatments have a direct impact on surface and near subsurface OH bond densities which greatly contribute to bonding energy changes. Better understanding of mechani...

Direct bonding energy is an important parameter for direct bonding applications as well as for mechanism elaboration. Thanks to its simplicity as well as for its simple result interpretation, double cantilever beam (DCB) under prescribed displacement is the most used technique to measure the direct bonding energy. But, as shown also in this study,...

Substrate engineering using Smart CutTM and Smart StackingTM for advanced LSIs is overviewed. For digital CMOS applications, planar fully-depleted (FD) SOI structure provides a realistic solution to bridge the technology gap between bulk CMOS and three-dimensional FD structures. Production of planar FD-SOI will be started soon in 28nm technology. R...

Bonding energy represents an important parameter for direct bonding applications as well as for the elaboration of physical mechanisms at bonding interfaces. Measurement of bonding energy using double cantilever beam (DCB) under prescribed displacement is the most used technique thanks to its simplicity. The measurements are typically done in stand...

The recent advances of the wafer direct bonding technology will be presented in this talk. The overview covers the technology perspective with respect to the fabrication of engineered substrates as well as 3D wafer stacking in light of the different applications for semiconductor industry.

The wafer direct bonding technique is very sensitive to water adsorbed on surfaces just before bonding; hence it is a useful way to characterize the impact of the trapped water and subsequently the wafer drying efficiency. We have focused this work on the water behavior at the bonding interface depending on the nature of the surface but also depend...

Smart Stacking™ is a wafer-to-wafer stacking technology of partially or fully processed wafers. This technology enables transferring very thin layers in a high volume manufacturing environment. The core technologies are surface conditioning, low temperature direct bonding and wafer thinning (figure 1). This technology is adapted for advanced semico...

An overview of the different metal bonding techniques used for 3D integration is presented. Key parameters such as surface preparation, temperature and duration of annealing, achievable wafer-to-wafer alignment and electrical results are reviewed. A special focus is given on direct bonding of patterned metal/dielectric surfaces. A mechanism for cop...

Layer splitting by helium and/or hydrogen and wafer bonding was applied for the transfer of thin single-crystalline ferroelectric oxide layers onto different substrates. The optimum conditions for achieving blistering/splitting after post-implantation annealing were experimentally obtained for LiNbO 3 , LaAlO 3 , SrTiO 3 single crystals and transpa...

Direct silicon wafer bonding is an attractive way to build up stacked structures. For applications, defect free bonding is required whatever the post bonding processes, which can include thermal treatment. Direct bonding processes are usually applied using hydrophilic surfaces. Thus water trapped at bonding interfaces can induce low temperature oxi...

This paper will focus on recent results of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking. We report on bonding quality, wafer-to-wafer alignment accuracy and electrical connectivity. Specific pre-bonding surface conditioning is necessary to insure high bonding quality of patterned Cu wafers. A particular concern is related to...

In this paper the integration challenges related to oxide-oxide bonding for wafer-to-wafer stacking technology are discussed. Furthermore, interface defectivity, wafer-to-wafer alignment and bond strength data are presented.

This article reports the capability and the recent development of optical profilometry for monitoring 3D integrated circuits. In particular, the capability to profile transparent film stacks, which was quite challenging, is now accessible with the Unifire optical profilometer from Nanometrics. It is demonstrated that the obtained information in ter...

Direct silicon wafer bonding is an attractive way to build up stacked structures. For applications, defect free bonding is required whatever the post bonding processes, which can include thermal treatment. Direct bonding processes are usually applied with hydrophilic surfaces. Thus water trapped at bonding interfaces can induce low temperature oxid...

The modern day wafer bonding is inspired by the pioneering work of Prof. Dr. Ulrich Gosele in science and technology of direct bonding. Gosele's research helped in understanding of the fundamental mechanisms and thus revealing the technological interest of this technology. The paper reviews the results of basic studies in the area of wafer direct b...

The microelectronic industry has arrived at a crossroads. There is the challenge of continued Moore's Law scaling and the ever-growing consumer demand for smaller, faster electronics with extended and new functionalities. 3D integration is a promising and fast-growing field that addresses the convergence of Moore's Law and more than Moore. 3D integ...

D integration is a promising and fast growing field that addresses the convergence of Moore's Law and more than Moore. D integration offers higher performance, higher density, higher functionality, smaller form factor, and potential cost reduction. With this emerging field, new and improved technologies will be necessary to meet the associated manu...

Interface defects formed during the wafer bonding process upon annealing have been studied. Based on the hydrogen diffusion in SiO ₂ and the stability of the bubbles at the bonding interface, models of the growth and further dissolution of the defects are presented. Considering the hydrogen diffusion through the interfacial oxide, diffus...

A model of the defect formation at the bonding interface upon annealing in silicon wafer bonding is proposed in this paper. It is shown that the formation of the bonding defects depends on the thickness of the silicon oxide at the bonding interface. A mechanism of thermal voids formation is suggested based on the hydrogen solubility in amorphous si...

The wafer bonding has been established as a key process used for the fabrication of silicon-on-insulator (SOI) substrates. In the present paper an overview of the fundamental aspects involved in the wafer bonding process is presented. The mechanisms of the silicon and silicon oxide bonding are discussed with an emphasis on the phenomenological mode...

Two-inch free-standing GaN wafers were implanted by 100 keV H+2 ions with a dose of 1.3 × 1017 cm−2 at room temperature. The hydrogen implantation induced damage in GaN extends between 230 to 500 nm from the surface as measured by cross-sectional transmission electron microscopy (XTEM). The wafer bow of the free-standing GaN wafers was measured usi...

Uniaxial strain on wafer-level was realised by mechanically bending and direct wafer bonding of Si wafers in the bent state followed by thinning one of the Si wafers by the smart-cut process. This approach is flexible and allows to obtain different strain values at wafer level in both tension and compression. UV micro-Raman spectroscopy was used to...

Direct wafer bonding between high-density-plasma chemical vapour deposited (HDP-CVD) oxide and thermal oxide (TO) has been investigated. HDP-CVD oxides, about 230 nm in thickness, were deposited on Si(0 0 1) control wafers and the wafers of interest that contain a thin strained silicon (sSi) layer on a so-called virtual substrate that is composed o...

Periodic arrays of strained Si (sSi) round nanopillars were fabricated on sSi layers deposited on SiGe virtual substrates by electron-beam lithography and subsequent reactive-ion etching. The strain in the patterned sSi nanopillars was determined using high-resolution UV micro-Raman spectroscopy. The strain relaxes significantly upon nanostructurin...

Fabrication of strained silicon on insulator (sSOI) substrates by wafer bonding and layer splitting is described in this paper. The sSi layer of 20 nm thickness is obtained on an 8 in. virtual substrate that consists of a plastically relaxed SiGe layer grown epitaxially on Si(001) by chemical vapor deposition (CVD). The plastic relaxation of the in...

Tensile strained Si (sSi) layers were epitaxially deposited onto fully relaxed Si0.78Ge0.22 (SiGe) epitaxial layers (4μm) on silicon substrates. Periodic arrays of 150nm×150nm and 150nm×750nm pillars with a height of 100nm were fabricated into the sSi and SiGe layers by electron-beam lithography and subsequent reactive ion etching. The strain in th...

Thin relaxed SiGe buffer layers with Ge contents of 23at% and 26at% and thicknesses in the range of 150 to 180 nm on Si(100) terminated with 6 nm Si were made by He ion implantation and annealing. Subsequent overgrowth of the thin buffers with thin strained Si cap layers with SiGe and strained Si reduced the threading dislocation and pile-up densit...

Different methods of preparing sSOI wafers have been analyzed. The initial virtual substrate wafers are characterized by a 17 - 20 nm thick strained silicon layer grown either on a thick relaxed SiGe layer on a graded buffer or on a thin SiGe buffer relaxed by He implantation. Bonding and layer transfer experiments using different oxide layers prov...

Four-inch InP wafers were implanted with 100 keV helium ions with a dose of 5×1016 cm−2 and subsequently annealed in air in the temperature range of 225–400°C in order to determine the blistering kinetics of these wafers. An Arrhenius plot of the blistering time as a function of reciprocal temperature revealed two different activation energies for...

Helium implantation-induced layer splitting of InP in combination with direct wafer bonding was utilized to achieve low temperature layer transfer of InP onto Si(1 0 0) substrates. InP(1 0 0) wafers with 4 inch diameter were implanted by 100 keV helium ions with a dose of 5 × 1016 cm−2. Then the as-implanted wafers were coated with a spin-on glass...

The formation of nanovoids upon high-dose hydrogen implantation and subsequent annealing in GaN is investigated by transmission electron microscopy. The epitaxial GaN layers on sapphire were implanted at room temperature with H2+ ions at 100 keV with a dose of 13×1016 cm−2. Cross section transmission electron microscopy investigations revealed that...

A systematic investigation of surface blister formation on GaN epitaxial layers implanted with 100 keV H2+ ions with a dose of 1.3×1017 cm-2 and annealed at various temperatures in the range of 350-700 °C was carried out. Two different activation energies were found for the formation of surface blisters: 1.79 eV in the lower temperature regime of 3...

The generation of defects (bubbles) in the interface of wafer pairs bonded by low-temperature bonding techniques was investigated. Statistical analyses of the size and distance distribution were used to describe the growth and dissolution mechanisms in different temperature ranges. Interfaces of wafer pairs pre-treated in a low-pressure plasma or b...

Semiconductor wafer direct bonding combined with mechanical grinding of the donor wafer and chemical etching of the remaining silicon as well as the SiGe layer is an alternative to the hydrogen-induced layer transfer (HILT). This process allows a larger window for thermal treatments. In combination with modified insulator layers also improvements o...

A systematic investigation of the hydrogen implantation-induced blister formation on the surface of Si0.78Ge0.22 when annealed in the temperature range of 300–700 °C was carried out. The strain-relaxed Si0.78Ge0.22 layers were grown epitaxially on 8-inch Si(1 0 0) substrates by reduced pressure chemical vapour deposition (RPCVD). These wafers were...

Wafer bonding of strained silicon (sSi) layer to oxidized Si (001) handle wafers is described in this paper. The sSi resides on two types of relaxed SiGe layers, a thick one (2μm in thickness) grown on top of a compositionally graded buffer and a thin one (∼180nm) for which He implantation and annealing are used to induce plastic strain relaxation...

Strained silicon devices provide for an enhanced carrier mobility compared to that of unstrained silicon devices of identical dimensions. The device performance gets even better when using strained silicon on insulator material. We report experimental procedures based on wafer bonding, smart cutting and selective chemical etching to obtain thin str...

Standard cold plasma systems operate at low pressure. This paper presents the so-called nanoPREP ambient pressure plasma technology based on the dielectric barrier discharge (DBD) principle with optimized design for wafer bonding applications. The parameters of the system are introduced, the characteristics of the plasma discharge are shown depende...

Wafer bonding of silicon wafers with various oxide layers to thermally oxidized Si handle wafers is described in this paper. We investigated plasma enhanced TEOS (PE-TEOS) and high density plasma (HDP) oxides, deposited with chemical vapor deposition (CVD). The bonding behavior of the CVD oxides was compared to the bonding of thermally grown oxides...

Wafer bonding of Si and Ge wafers activated by dielectric barrier discharge (DBD) is presented in this paper. After low temperature annealing of the bonded pairs no interface bubbles are detected. One reason is the reduction of the carbon concentration on the surfaces treated by DBD. The activation process does not increase the surface micro-roughn...

Two different types of oxide layers (a low-temperature oxide and an ultrathin thermal oxide) were deposited on strained silicon (sSi) and bonded hydrophilically to oxidized Si(001) handle wafers. To enhance the bonding energy, the bonded wafers were annealed at 300°C for 5 h and subsequently at 500°C for 2 h. The quality of the bonded interface was...

A low temperature direct bonding method that is CMOS compatible is described. The method is applied in the manufacturing of advanced spatial light modulators with a matrix of up to 512 × 2048 individually addressable monocrystalline silicon mirrors. The key processing step is the layer transfer of a 260nm thick silicon membrane from an SOI wafer to...

In recent years a major effort has been put into achieving integration of functional materials into semiconductor technology. Among functional materials ferroelectrics are an important class of materials, exhibiting a large spectrum of properties and effects including the piezoelectric effect, pyroelectric effect, electro-optic effect, spontaneous...

Transfer of GaAs layers onto Si by helium and/or hydrogen implantation and wafer bonding was investigated. The optimum conditions for achieving blistering/splitting only after postimplantation annealing were experimentally obtained. It was found that specific implantation conditions induce large area exfoliation instead of blistering after annealin...

Layer splitting by helium and/or hydrogen implantation and wafer bonding was applied to transfer thin single-crystalline ferroelectric layers onto different substrates. The optimum conditions for achieving blistering/splitting after post-implantation annealing were experimentally obtained for LiNbO3, LaAlO3, SrTiO3 single crystals and PLZT ceramic....