I. Garcia-Vargas

Universidad de Sevilla | US · Architecture and Computer Technology

This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing chips based on cellular neural networks. SIRENA includes capabilities for: (a) the description of nominal and non-ideal operation of CNN analogue circuitry at the behavioural level; (b) performing realistic simulations of the tran...

This letter proposes a new model of state machine called Finite Virtual State Machine (FVSM). A memory-based architecture and a procedure for generating FVSM implementations from Finite State Machines (FSMs) are presented. FVSM implementations provide advantages in speed over conventional RAM-based FSM implementations. The results of experiments pr...

In this paper, we introduce a new problem related to bipartite graphs called minimum maximal k-partial-matching (MMKPM) which has been modelled by using a relaxation of the concept of matching in a graph. The MMKPM problem can be viewed as a generalization of the classical Hitting Set and Set Cover problems. This property has been used to prove tha...

A new approach for ROM implementation of finite state machines (FSM) is proposed, based on the selection of a subset of inputs in each state using multiplexers. This technique has been applied to different FSM standard benchmarks and very good results have been obtained.

The model called Finite State Machine with Input Multiplexing (FSMIM) was proposed as a mechanism for implementing Finite State Machines (FSMs) using ROM memory. This paper presents a novel approach for achieving more efficient FSMIM implementations in Field Programmable Gate Array (FPGA) devices. The aim of the proposed approach is to obtain furth...

This paper proposes a new technique for implementing Finite State Machines (FSMs) in Field Programmable Gate Arrays (FPGAs). The proposed approach extends the called column compaction in two ways. First, it is applied to the state-encoding bits in addition to the outputs, allowing a reduction in the number of logic functions required both by the st...

Finite State Machines with Input Multiplexing (FSMIMs) were proposed in previous work as a technique for efficient mapping Finite State Machines (FSMs) into ROM memory. In this paper, we present new contributions to the optimization process involved in the implementation of FSMIMs in Field Programmable Gate Array (FPGA) devices. This process consis...

Current Field Programmable Gate Arrays (FPGAs) provide fast routing links and special logic to perform carry operations; however, these resources can also be used to implement non-arithmetic circuits. In this paper, a new approach for mapping logic functions onto carry chains is presented. Unlike other approaches, the proposed technique can be appl...

This brief explores the optimization of distributed-ROM-based Finite State Machine (FSM) implementations as an alternative to conventional implementations based on Look-Up Tables (LUTs). In distributed-ROM implementations, LUTs with constant output value (called constant LUTs) and LUTs with the same content (called equivalent LUTs) can be saved. We...

A Binary-Tree-based Finite State Machine (BT-FSM) is a state machine with a 1-bit input signal whose state transition graph is a binary tree. BT-FSMs are useful in those application areas where searching in a binary tree is required, such as computer networks, compression, automatic control, or cryptography. This paper presents a new architecture f...

This work is focused on the problem of designing efficient reconfigurable multiplexer banks for RAM-based implementations of reconfigurable state machines. We propose a new architecture (called combination-based reconfigurable multiplexer bank, CRMUX) that use multiplexers simpler than that of the state-of-the-art architecture (called variation-bas...

Finite state machines with input multiplexing (FSMIMs) have been proposed in previous works as a technique for efficient mapping FSMs into ROM memory. In this paper, we propose a new architecture for implementing FSMIMs, called FSMIM with state-based input selection, whose goal is to achieve a further reduction in memory usage. This paper also desc...

This paper discusses the problem of minimizing the reconfiguration cost of some types of reconfigurable systems. A formal definition of the problem and a proof of its NP-completeness are provided. In addition, an Integer Linear Programming formulation is proposed. The proposed problem has been used for optimizing a design stage of Finite Virtual St...

Tool to generate implementations of FSMIM from FSM. Implements the techniques presented in the publication. A previous version of the tool has been used for the experimental studies. It is distributed under the GNU License as an Octave package. This archive include: * fsm2fsmim-0.1.6.tar.gz: Octave package. * Quick installation guide for non-Octave...

Tool to generate implementations of FSMIM from FSM. Implements the techniques presented in the publication. A previous version of the tool has been used for the experimental studies. It is distributed under the GNU License as an Octave package. This archive include: * fsm2fsmim-0.1.6.tar.gz: Octave package. * Quick installation guide for non-Octave...

This paper presents a study of performance of RAM-based implementations in FPGAs of Finite State Machines (FSMs). The influence of the FSM characteristics on speed and area has been studied, taking into account the particular features of different FPGA families, like the size of LUTs, the size of memory blocks, the number of embedded multiplexer le...

In this paper, we present a HDL description of a RAM with asymmetric port widths which allows read and write operations with different data size. This RAM is suitable for implementing run-time reconfigurable systems in FPGA. The proposed RAM specification has been tested with different target devices.

This work presents a technique for the resource optimization of input multiplexed ROM-based Finite State Machines. This technique exploits the don't care value of the inputs to reduce the memory size as well as multiplexer complexity. This technique has been applied to a publicly available FSM benchmarks and implemented in a low-cost FPGA. Results...

Address-event-representation (AER) is a communication protocol that emulates the nervous system's neurons communication, and that is typically used for transferring images between chips. It was originally developed for bio-inspired and real-time image processing systems. Such systems may consist of a complicated hierarchical structure with many chi...

This paper addresses the problems arising in the calculation of numerical references (network function coefficients), essential for an appropriate error control in simplification before and during generation algorithms for symbolic analysis of large analog circuits. The conventional polynomial interpolation method reveals to be unable to handle the...

SIRENA is a general simulation environment for artificial neural networks, with emphasis towards CNNs. A special interest has been placed in allowing the simulation and modelling of the non-ideal effects expected from VLSI implementations. SIRENA allows the simulation of CNNs in greater detail than conventional CNN simulators, and much more efficie...