Hugues Cassé

Hugues Cassé
Paul Sabatier University - Toulouse · IRIT

PhD

About

54
Publications
7,213
Reads
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848
Citations
Introduction
Interested in static analysis for WCET (Worst Case Execution Computation) for hardware analysis, data flow analysis, partial computation. Main developer and designer of OTAWA tool for WCET computation.
Additional affiliations
September 2004 - present
University of Toulouse
Position
  • Professor (Assistant)
September 2004 - present
Paul Sabatier University - Toulouse III
Position
  • Lecturer

Publications

Publications (54)
Article
We present MINOTAuR, an open-source RISC-V core designed to be timing predictable, i.e., free of timing anomalies: this property enables a compositional timing analysis in a multicore context. MINOTAuR features speculative execution: thanks to a specific design of its pipeline, we formally prove that speculation does not break timing predictability...
Preprint
Worst-Case Execution Time (WCET) is a key component for the verification of critical real-time applications. Yet, even the simplest microprocessors implement pipelines with concurrently-accessed resources, such as the memory bus shared by fetch and memory stages. Although their in-order pipelines are, by nature, very deterministic, the bus can caus...
Article
Due to the dynamic behaviour of acceleration mechanisms such as caches and branch predictors, static Worst-Case Execution Time ( wcet ) analysis methods tend to scale poorly to modern hardware architectures. As a result, a trade-off must be found between the duration and the precision of the analysis, leading to an overestimation of the wcet bounds...
Conference Paper
We present MINOTAuR, a timing predictable open source RISC-V core based on the Ariane core. We first modify Ariane in order to make it timing predictable following the approach used to design the SIC processor. We prove that the instruction parallelism in the Ariane core does not prevent from enforcing timing predictability. We further relax restri...
Preprint
Full-text available
We present a static analysis framework for real-time task systems running on multi-core processors. Our method analyzes tasks in isolation at the binary level and generates worst-case timing and memory access profiles. These profiles can then be combined to perform an interference analysis at the task system level, as part of a multi-core Worst-Cas...
Conference Paper
Full-text available
We introduce a unified wcet analysis and scheduling framework for real-time applications deployed on multicore architectures. Our method does not follow a particular programming model, meaning that any piece of existing code (in particular legacy) can be re-used, and aims at reducing automatically the worst-case number of timing interferences betwe...
Conference Paper
Static analysis requires the full knowledge of the overall program structure. The structure of a program can be represented by a Control Flow Graph ( cfg ) where vertices are basic blocks ( bb ) and edges represent the control flow between the bb . To construct a full cfg , all the bb as well as all of their possible targets addresses must be found....
Conference Paper
Full-text available
The presence of infeasible paths in a program is a source of imprecision in the Worst-Case Execution Time (WCET) analysis. Detecting, expressing and exploiting such paths can improve the WCET estimation or, at least, improve the confidence we have in estimation precision. In this article, we propose an extension of the FFX format to express conflic...
Article
The EC project parMERASA (Multicore Execution of Parallelized Hard Real-Time Applications Supporting Analyzability) investigated timing-analyzable parallel hard real-time applications running on a predictable multicore processor. A pattern-supported parallelization approach was developed to ease sequential to parallel program transformation based o...
Article
Worst-Case Execution Time (WCET) is a key component to check temporal constraints of realtime systems. WCET by static analysis provides a safe upper bound. While hardware modelling is now efficient, loss of precision stems mainly in the inclusion of infeasible execution paths in the WCET calculation. This paper proposes a new method to detect such...
Article
To reduce complexity while computing an upper bound on the worst-case execution time, static WCET analysis performs over-Approximations. This feeds the general feeling that static WCET estimations can be far above the real WCET. This feeling is strengthened when these estimations are compared to measured execution times: generally, it is very unlik...
Conference Paper
In a hard Real-Time (HRT) domain such as avionics, the high application performance is as important as delivering a predictable execution time. More precisely, the performance is defined by the application Worst-Case Execution Time (WCET). A common practice to boost the application performance in general purpose computing is by parallelisation and...
Conference Paper
WCET calculus is nowadays a must for safety critical systems. As a matter of fact, basic real-time properties rely on accurate timings. Although over the last years, substantial progress has been made in order to get a more precise WCET, we believe that the design of the underlying frameworks deserve more attention. In this paper, we are concerned...
Conference Paper
Full-text available
Engineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in performance is expected by parallelizing hard real-time applications and running them on an embedded multi-core processor, which enables combining the requirements for high-...
Conference Paper
Full-text available
The analysis of the worst-case execution times is necessary in the design of critical real-time systems. To get sound and precise times, the WCET analysis for these systems must be performed on binary code and based on static analysis. OTAWA, a tool providing WCET computation, uses the Sim-nML language to describe the instruction set and XML files...
Article
Full-text available
Temporal property verification is utterly important to ensure safety of critical real-time systems. A main component of this verification is the computation of Worst Case Execution Time (WCET) that requires, in turn, the determination of loop bounds. Although a lot of efforts have been performed in this domain, it remains relatively common cases wh...
Conference Paper
Full-text available
In order to ensure safety of critical real-time systems it is crucial to verify their temporal properties. Such a property is the Worst-Case Execution Time (WCET), which is obtained by architecture-dependent timing analysis and architecture-independent flow fact analysis. In this article we present a WCET annotation language which is able to expres...
Article
Full-text available
Robots are more and more used in very diverse situations (services to persons, military missions, crisis management, . . . ) in which robots must give some guarantees of safety and reliability. To be really integrated in everyday life, robots must fulfil some requirements. Among these requirements, we focus on the nonfunctional requirements on embe...
Article
Full-text available
In this paper, we propose a mechanism allowing to evaluate the schedulability of a robotic software architec-ture, and then validate its real-time properties. The robotic software architecture is described through a Domain Speciic Language (DSL), MAUVE, that allows to model communicating components. The evaluation of schedulability of the architect...
Conference Paper
Full-text available
In order to be able to use multicore COTS hardware in critical systems, we put forward a time-oriented execution model and provide a general framework for programming and analysing a multicore compliant with the execution model.
Article
Multi-cores are the contemporary solution to satisfy high performance and low energy demands in general and embedded computing domains. However, currently available multi-cores are not feasible to be used in safety-critical environments with hard real-time constraints. Hard real-time tasks running on different cores must be executed in isolation or...
Article
Full-text available
Typical constraints on embedded systems include code size limits, upper bounds on energy consumption and hard or soft deadlines. To meet these requirements, it may be necessary to improve the software by applying various kinds of transformations like compiler optimizations, specific mapping of code and data in the available memories, code compressi...
Article
Full-text available
The Merasa project aims to achieve a breakthrough in hardware design, hard real-time support in system software, and worst-case execution time analysis tools for embedded multicore processors. The project focuses on developing multicore processor designs for hard real-time embedded systems and techniques to guarantee the analyzability and timing pr...
Conference Paper
Full-text available
In order to ensure that timing constrains are met for a Real-Time Systems, a bound of the Worst-Case Execution Time (WCET) of each part of the system must be known. Current WCET computation methods are applied on whole programs which means that all the source code should be available. However, more and more, embedded software uses COTS (Components...
Conference Paper
Full-text available
The analysis of worst-case execution times has become mandatory in the design of hard real-time systems: it is absolutely necessary to know an upper bound of the execution time of each task to determine a task schedule that insures that deadlines will all be met. The OTAWA toolbox presented in this paper has been designed to host algorithms resulti...
Conference Paper
Full-text available
The SoCKET project (SoC<sup>1</sup> toolKit for critical Embedded sysTems)<sup>2</sup> gathers industrial and academic partners to address the issue of design methodologies for critical embedded systems. They work towards the definition of a “seamless” design flow which integrates qualification and certification, from the system level to integrated...
Conference Paper
Full-text available
Multi-cores are the contemporary solution to satisfy high performance and low energy demands in gen- eral and embedded computing domains. However, currently available multi-cores are not feasible to be used in safety- critical environments with hard real-time constraints. Hard real-time tasks running on different cores must be executed in isolation...
Conference Paper
Full-text available
This article presents the results of experimenting our OTAWA tool to compute WCETs on a real automotive embedded application. First, we analyze the application (C source generated from Simulink models) and exhibit specific properties and their implication on the WCET computation. Then, two very different embedded processor architectures are tested...
Article
Full-text available
Code compression techniques might be useful to meet code size constraints in embedded systems. In the average case, the impact of code compression on the performance is double-edged: on one side, the number of accesses to memory hierarchy is reduced because several instructions are coded in a single word, and this is likely to reduce the execution...
Conference Paper
Full-text available
Instruction-set simulators (ISS) are more and more used in design space exploration and functional software testing. Furthermore, cycle-accurate simulators are often made of a functional coupled to a timing simulator. Research about ISS generators is not new but most often addresses only simple instruction sets (i.e. RISC). This paper describes tec...
Conference Paper
Full-text available
Validation of embedded hard real-time systems requires the computation of the Worst Case Execution Time (WCET). Although these systems make more and more use of Components Off The Shelf (COTS), the current WCET computation methods are usually applied to whole programs: these analysis methods require access to the whole system code, that is incompat...
Article
Full-text available
These last years, many researchers have proposed solutions to estimate the Worst-Case Execution Time of a critical application when it is run on modern hardware. Several schemes commonly implemented to improve performance have been considered so far in the context of static WCET analysis: pipelines, instruction caches, dynamic branch predictors, ex...
Conference Paper
Full-text available
One of the important steps in processing the worst case execution time (WCET) of a program is to determine the loops upper bounds. Such bounds are crucial when verifying real-time systems. In this paper, we propose a static loop bound analysis which associates flow analysis and abstract interpretation. It considers binary operators (+, -, *, ) for...
Conference Paper
Full-text available
The methods for worst case execution time (WCET) computation need to analyse both the control flow of the task, and the architecture effects involved by the hosting architecture. An important architectural effect that needs to be predicted is the instruction cache behavior. This prediction is commonly performed by assigning to each program instruct...
Conference Paper
Full-text available
In hard real-time applications, Worst Case Execution Time (WCET) is used to check time constraints of the whole system but is only computed at the task level. As most WCET computation methods assume a conservative approach to handle the processor state before the execution of a task, the inter-task analysis of long effect hardware features should i...
Article
Full-text available
Le développement d'un simulateur de processeur est long et fastidieux. Découpler la partie fonctionnelle (émulation) de la partie structure (analyse des temps de traitement) permet de réutiliser plus facilement du code existant (principalement le code d’émulation, les jeux d’instructions évoluant moins vite que les architectures matérielles). Dans...
Conference Paper
Full-text available
The current Worst Case Execution Time (WCET) computation methods are usually applied to whole programs, this may drive to scalability limitations as the program size becomes bigger. A solution could be to split programs into components that could support separated partial analyses to decrease the computation time. The componentization is also consi...
Article
Full-text available
Implicit Path Enumeration Technique (IPET) is currently largely used to compute Worst Case Execution Time (WCET) by modeling control flow and architecture using integer linear programming (ILP). As precise architecture effects requires a lot of constraints, the super-linear complexity of the ILP solver makes computation times bigger and bigger. In...
Article
Full-text available
Following the successful WCET Tool Challenge in 2006, the second event in this series was organized in 2008, again with support from the ARTIST2 Network of Excellence. The WCET Tool Challenge 2008 (WCC'08) provides benchmark programs and poses a number of "analysis problems" about the dynamic, run-time properties of these programs. The participants...
Conference Paper
Full-text available
In hard real-time applications, WCET is used to check time constraints of the whole system but is only computed at the task level. While most WCET computation methods assume a conservative approach to handle the processor state before the execution of a task, the inter-task analysis of long effect hardware facilities should improve the accuracy of...
Article
Full-text available
This paper presents PapaBench, a free real-time benchmark and compares it with the existing benchmark suites. It is designed to be valuable for experimental works in WCET computation and may be also useful for scheduling analysis. This bench is based on the Paparazzi project that represents a real-time application, developed to be embedded on diffe...
Article
Full-text available
OTAWA is a generic framework for the computation of Worst-Case Execution Time. Delivered under the LGPL licence, it provides a versatile environment with services for static analyses on executables.
Article
Full-text available
Instruction Level Simulation has received big attention as it allows out-of-silicium test and hardware exploration. In this paper, we present GLISS2, the second release of a simulator generator based on the NML ADL. Thanks to the implementation of a set of optimization techniques (acceleration in memory emulation, caches for the decode step and blo...
Article
Full-text available
Following the successful WCET Tool Challenge in 2006, the second event in this series was organized in 2008, again with support from the ARTIST2 Network of Excellence. The WCET Tool Challenge 2008 (WCC'08) provides benchmark programs and poses a number of "analysis problems" about the dynamic, run­time properties of these programs. The participants...
Article
Full-text available
In this article, we present OTAWA, a framework for computing the Worst Case Execution Time of a program. From its design, it provides an extensible and open architecture whose objective is the implementation of existing and future static analyses for WCET computation. Inspired by existing generic tools, it is based on an architecture abstraction la...

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