Hansraj Guhilot

Hansraj Guhilot
K C College of Engineering and Management Studies and Research, Thane(E) 400607

About

31
Publications
6,644
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84
Citations
Introduction
Skills and Expertise
Additional affiliations
September 2013 - March 2015
Excelssior Education Society's K C College of Engineering and Management Studies and Research, Thane(E) 400607
Position
  • Professor and Principal

Publications

Publications (31)
Article
Full-text available
A 13-bit Time to Digital Converter is implemented using multiphase clock technique. Xilinx’s Virtex 5 FPGA platform is used to realize the TDC architecture. One PLL within the FPGA works as a clock synthesizer to multiply the reference clock to 500MHz. Then the combination of PLL and DLL topologies are used to generate 16 three phases of clock, sep...
Article
This work presents a comprehensive literature review on different topologies of time‐to‐digital converters (TDCs). A brief history, applications, classification, characterization, and working principle of each TDC are mentioned. A survey of both Field Programmable Gate Array (FPGA) and Application‐Specific Integrated Circuit (ASIC) architectures is...
Article
Full-text available
Fully digital time-domain temperature sensors are designed and placed at five different positions within FPGA. Five tiny pulse-generators are used as five temperature sensors. Using manual floor-planning four sensors are placed at four different corners and one at center. Single 9-bit Time to Digital Converter is utilized for digital output coding....
Conference Paper
Full-text available
This paper presents a high resolution Vernier Time to Digital Converter(TDC) implemented on low cost FPGA. A novel way to utilize PLLs present within FPGA presented here. The technique includes generating multiphase clocks and selecting one among them to minimize the error. With this the maximum error is ¼T CLK rather than T CLK. The BIST circuitry...
Article
Full-text available
In this paper we have discussed the design constraints of a computer vision based mobile robot and processing the real time video received from the mobile robot. The focus is on applying DWT algorithm on the real time video so that memory size required for storage is reduced. The mobile robot which feeds in the live steaming of video of surrounding...
Conference Paper
In this paper, a ADC using pulse shrinking TDC is proposed. The proposed ADC include a Pulse forming circuit, Pulse shrinking TDC and a compatible Counter. Initially, input voltage is converted to a proportional time pulse and then digitized using Time to Digital Converter (TDC). We present a fully-integrated Time-to-Digital Converter based on cycl...
Article
Full-text available
A review of comparison of various types of ADC's with Time Based ADC.
Article
Full-text available
Line multiplier is a novel way of multiplication. In Digital signal processing operation multiplication is heavily used arithmetic operation and performance of processor depends on multiplier performance. So designing a low power multiplier is essential. In this paper line multiplier is implemented which is adder-less so easy to implement. Also no...
Conference Paper
Fully digital time-domain temperature sensors are designed and placed at five different positions within FPGA. Five tiny pulse-generators are used as five temperature sensors. Using manual floor-planning four sensors are placed at four different corners and one at centre. Single 9-bit Time to Digital Converter is utilized for digital output coding....
Conference Paper
This paper presents a contactless reprogrammable position measurement system designed using the HDL(hardware description language) and realized in hardware using the field programmable array (FPGA). The proposed system is able to measure the contactless position at various locations with each of them to its accuracy. It is used to measure pressure...
Conference Paper
An improved range with new principle is developed for contactless position sensing using piezoresistive position sensor. An attempt is made in devising a transducer based on piezoresistive principle for contactless position measurement. The sensor has non-contact and non-optical nature which is advantageous in many applications. However, in order t...
Conference Paper
Full-text available
We present an area efficient Time to Digital Converter (TDC) based on Vernier Principle yielding a high resolution of nearly 5ps. The TDC architecture reported in this paper uses Nutt Interpolation method i.e. comprises of coarse measurement using system clock and two controllable ring oscillators for fine measurement. Ring oscillators used in this...
Chapter
With the growing popularity of Internet and extensive use of E-mail as a communication media, the volume of Spam mails has seen to be growing at a phenomenal rate. The growing volume of Spam mails as well as their mutating nature annoys people and affects work efficiency significantly. The unsolicited emails or Spam’s used to be deliberated of as j...
Chapter
Embedding a soft IP core inside an FPGA has many advantages such as customization, design reuse, accelerating the design cycle and narrowing the time to market window thereby enhancing the productivity. In view of all the above mentioned advantages, the FPGA based systems are now penetrating the embedded arena which has marked the take off of the c...
Chapter
In an increasingly digital domain of applications, the Digital Signal Processing (DSP) has become inevitable. With the outside environment predominantly analog, its conversion into the digital domain in order to facilitate the benefits of the matured DSP technology is also mandatory. Many a times the analog to digital converter performance becomes...
Chapter
This chapter presents an FPGA-based ECG system with telemonitoring facility. There are several methods of recording and transmitting ECG signals. A classical recording in health centers, then ambulatory ECG recordings and tele­metry monitoring the patient in and round medical center. The system presented in this chapter has a provision to transmit...
Article
Full-text available
Development of monolithic all nMOS Automatic Quenching and Reset Circuit (AQRC) for chlorophyll fluorescence SPAD sensor is reported using Microwind 3.1 and LTSpice version IV for 120 nm technology. An efficient bio-signal acquisition with single-photon counting facility, fast quenching, and reset is described using only ten nMOS transistors. The u...
Article
Full-text available
An active inductor variable load quenching circuit monolithically implemented for sensing chlorophyll fluorescence and other sensor applications like bioluminescence, tomography, and DNA fingerprints is reported for the first time in this paper. An efficient biosignal acquisition with single-photon counting facility and fast quenching and reset for...
Conference Paper
Full-text available
We present an area efficient Time to Digital Converter (TDC) yielding a high resolution of nearly 10ps. The TDC architecture reported in this paper comprises of coarse measurement using system clock and two controllable oscillators for fine resolution measurement. The reported improved resolution is attributed to the difference in their frequencies...
Conference Paper
Power consumption and stability happen to be of great concern in the deep-submicron SRAM cell design. In this paper, the design and functionality of a novel ultra low power stable SRAM cell is discussed which addresses power minimization as well as stability against large variation in temperature which is ideally suited for space applications. This...
Article
Full-text available
Development of monolithic all nMOS Automatic Quenching and Reset Circuit for chlorophyll fluorescence SPAD sensor is reported using Microwind 3.1 and LT Spice version IV for 120nm technology. An efficient bio-signal acquisition with single photon counting facility and fast quenching and reset is proposed circuit with a fast time to voltage converte...
Article
Full-text available
This paper describes a novel analog front end sensor signal processing block for applications like Bio-fluorescence, tomography, DNA fingerprints. Along with the principle a detailed design is presented in 120nm technology. Analog simulations are done using LT spice version IV and Layout is done using Microwind 3.1 this sensor design differs from a...
Conference Paper
Full-text available
IEEE Xplore Abstract ­ A CMOS VLSI implementation of Mean Life Time (MLT) Detector for Bio­luminescence Sensor Publisher: IEEE This paper describes a novel analog front end sensor signal processing block for applications like Bio­ fluorescence, tomography, DNA fingerprints. Along with the principle a detailed design is presented in 120 nm technolog...
Conference Paper
Full-text available
The present paper communicates development of a novel biosensor interface for detection of chlorophyll contents in any leaf. It presents development of a monolithically integrated CMOS chip for many biological processes of agricultural electronics in general and chlorophyll detection in particular. Chlorophyll content is detected using a novel anis...
Article
Full-text available
The purpose of this paper is to develop a CMOS preprocessor for bio parameter sensing applications using analog building blocks such as operational amplifiers & active resistors. The main objectives of this activity were to design a operational amplifier with temperature compensation & a VLSI active floating resistor of higher linearity with simple...
Article
The purpose of this paper is to develop a CMOS preprocessor for bio parameter sensing applications using analog building blocks such as operational amplifiers & active resistors. The main objectives of this activity were to design a operational amplifier with temperature compensation & a VLSI active floating resistor of higher linearity with simple...

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