H.-S. Philip Wong

• Stanford University

As AI workloads drive soaring memory requirements, there is a need for higher-density on-chip memory for domain-specific accelerators that goes beyond what current SRAM technology can provide. We motivate that algorithms and application behavior should guide the composition of heterogeneous on-chip memories. However, there has been little work in f...

In this work, we address the off-state leakage current challenge, while simultaneously demonstrating high drive current per CNT, in NMOS and PMOS carbon nanotube field-effect transistors (CNFETs). Increasing the bandgap from 0.6 to 0.85 eV reduces the minimum current from 10–8 A/μm to 10–11 A/μm at VDS = −0.5 V with a channel length of 50 nm. By ut...

Dynamic random access memory (DRAM) density scaling can be enabled by monolithically stacking DRAM cells in the vertical direction (3-D DRAM). However, there is no analysis of whether 3-D DRAM with horizontal bitline (HBL) or vertical bitline (VBL) is more scalable. Here, we evaluate the signal margin and bitcell density of HBL versus VBL 3-D DRAM...

Amorphous oxide semiconductors are gaining interest for logic and memory transistors compatible with low-temperature fabrication. However, their low thermal conductivity and heterogeneous interfaces suggest that their performance may be severely limited by self-heating, especially at higher power and device densities. Here, we investigate the high-...

Large Language Models (LLMs) serve as critical foundations for a wide range of generative AI applications, which demand substantial memory and storage. The advent of monolithic 3D stackable DRAM, offering cost-effective vertical scaling akin to 3D NAND, presents a promising solution to this challenge. This article conducts a comparative analysis of...

The future memory is massive, diverse, and tightly integrated with computing. This research presents tight integration, both physically and architecturally, of two on-chip memory technologies, resistive switching random access memory (RRAM) and gain cell (GC) memory. HfO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3....

Low-dimensional 1D and 2D materials hold promise as candidate channel materials for highly scaled and high-performance transistors beyond the limits of silicon-based transistors. This talk will first motivate transistors built on low-dimensional channels due to the significant speed, energy efficiency, and transistor density benefits enabled by the...

The energy and delay consumed by the off-chip memory (DRAM) and memory-to-logic chip data movement becomes the bottleneck (known as the memory wall) for the computing systems nowadays, especially for abundant-data computing and neural network accelerators. Larger on-chip memory capacity with high bandwidth can be a solution, yet it is difficult to...

We offer design guidelines with a top–down and bottom–up design approach for oxide semiconductor (OS) transistors, optimized for gain cell memory on a logic platform. With high-density, high-bandwidth on-chip gain cell memory, deep neural network (DNN) accelerator execution times can be shortened by 51–66%, by minimizing access to off-chip dynamic...

Many innovations across the system stack – from algorithms and architectures to circuits, devices, fabrication processes, and materials – will provide large synergistic benefits at the system level. While conventional wisdom optimizes for cost per transistor and economizes on the use of transistors, other optimization targets are becoming highly re...

Semiconducting single‐walled carbon nanotube (CNT) is a promising candidate as a channel material for advanced logic transistors, attributed to the ultra‐thin 1‐nm cylindrical geometry, high mobility, and high carrier injection velocity. However, the presence of undesired CNT bundles in the CNT arrays for wafer‐scale device fabrication, even when u...

The 2-D transition metal dichalcogenides (2-D TMDs) have emerged as a promising channel material for postsilicon applications for their ultrathin structure and excellent electrostatic control. However, achieving low contact resistance at scaled contact length remains a challenge. This article overcomes this challenge through optimized deposition of...

Amorphous oxide semiconductors (AOSs) are receiving increased attention for electronics requiring low fabrication temperatures, but concerns remain about their stability. Here, we fabricate thin ( $\sim$ 4 nm) indium tin oxide (ITO) field-effect transistors (FETs) with three back-gate dielectrics (HfO $_{\text{2}}$ , Al $_{\text{2}}$ $\text{O}_...

Low-dimensional semiconductors such as one-dimensional carbon nanotubes could be used to shrink the gate length of metal–oxide–semiconductor field-effect transistors (MOSFETs) below the limits of silicon-based transistors. However, the development of industry-compatible doping strategies and polarity-control methods for such systems is challenging....

Resistive random-access memory (RRAM) is a promising technology for data storage and neuromorphic computing; however, cycle-to-cycle and device-to-device variability limits its widespread adoption and high-volume manufacturability. Improving the structural accuracy of RRAM devices during fabrication can reduce these variabilities by minimizing the...

We report ultrathin ( ${\sim }4$ nm) channel indium tin oxide (ITO) transistors, comparing different precursors for atomic layer deposition (ALD) of the Al2O3 top-gate dielectric, and analyze the role of dielectric deposition on transistor performance and gate bias stress stability. Water-based ALD leads to very negative threshold voltage ( ${V}_{...

The field of design and design automation of micro/nano circuits and systems promotes interdisciplinary research spanning computer science, computer engineering, and electrical engineering. This field has created key technologies without which it would be impossible to achieve advances in information processing, which is an inseparable part of our...

Phase-change superlattices with nanometer thin sublayers are promising for low-power phase-change memory (PCM) on rigid and flexible platforms. However, the thermodynamics of the phase transition in such nanoscale superlattices remain unexplored, especially at ultrafast scanning rates, which is crucial for our fundamental understanding of superlatt...

Recent technology development of logic devices based on 2-D semiconductors such as MoS $_{\text{2}}$ , WS $_{\text{2}}$ , and WSe $_{\text{2}}$ has triggered great excitement, paving the way to practical applications. Making low-resistance p-type contacts to 2-D semiconductors remains a critical challenge. The key to addressing this challenge is...

For many decades, progress in computing hardware has been closely associated with CMOS logic density, performance, and cost. As such, slowdown in 2-D scaling, frequency saturation in CPUs, and increased cost of design and chip fabrication for advanced technology nodes since the early 2000s have led to concerns about how semiconductor technology may...

Low voltage and low off-current selectors are needed to meet the requirements for cross-point array architectures in embedded memories. Chalcogenide-based selectors have been widely studied for such applications, but no single material system has yet demonstrated all the specifications required for integration with nonvolatile memory. This article...

We demonstrate a back-end-of-line (BEOL) compatible 2T gain cell consisting of n-type indium-tin-oxide (ITO) MOSFET as a write transistor and p-type carbon nanotube (CNT) MOSFET as a read transistor. The opposite polarities help counteract the capacitive coupling in gain cells operating with voltage sensing: the drop of the storage node voltage due...

Semiconducting carbon nanotubes are robust molecules with nanometer-scale diameters that can be used in field-effect transistors, from larger thin-film implementation to devices that work in conjunction with silicon electronics, and can potentially be used as a platform for high-performance digital electronics as well as radio-frequency and sensing...

Hafnia-based ferroelectric thin films are promising for semiconductor memory and neuromorphic computing applications. Amorphous, as-deposited, thin-film binary alloys of HfO2 and ZrO2 transform to the metastable, orthorhombic ferroelectric phase during post-deposition annealing and cooling. This transformation is generally thought to involve format...

Resistance drift in phase change memory (PCM) reduces the accuracy of analog computing applications such as neural network inference. Recently, PCMs based on superlattice (SL) phase change layers have shown low resistance drift, however the origin of this low drift remains unexplored. Here, we uncover that resistance drift in SL-PCM based on altern...

Carbon nanotube field effect transistors (CNFETs) have potential applications in future logic technology as they display good electrostatic control and excellent transport properties. However, contact resistance and leakage currents could limit scaling of CNFETs. Non-equilibrium Green’s function (NEGF) simulation investigates that coupling between...

Superlattice (SL) phase change materials have shown promise to reduce the switching current and resistance drift of phase change memory (PCM). However, the effects of internal SL interfaces and intermixing on PCM performance remain unexplored, although these are essential to understand and ensure reliable memory operation. Here, using nanometer-thi...

Low-dimensional (low-D) semiconductors such as carbon nanotubes (CNTs) and 2-D materials are promising channel materials for nanoscale field-effect transistors (FETs) due to their superior electrostatic control. However, classical scale length theory (SLT) does not incorporate the effect of channel extensions, which becomes crucial for thin channel...

Gradual switching between multiple resistance levels is desirable for analog in-memory computing using resistive random-access memory (RRAM). However, the filamentary switching of $HfO_x$-based conventional RRAM often yields only two stable memory states instead of gradual switching between multiple resistance states. Here, we demonstrate that a th...

Ferroelectric switching is demonstrated in CeO2‐doped Hf0.5Zr0.5O2 (HZCO) thin films with application in back‐end‐of‐line compatible embedded memories. At low cerium oxide doping concentrations (2.0–5.6 mol%), the ferroelectric orthorhombic phase is stabilized after annealing at temperatures below 400 °C. HZCO ferroelectrics show reliable switching...

Semiconductor innovation drives improvements to technologies that are critical to modern society. The country that successfully accelerates semiconductor innovation is positioned to lead future semiconductor-driven industries and benefit from the resulting economic growth. It is our view that a next generation infrastructure is necessary to acceler...

Carbon nanotube (CNT) transistors exemplify the fundamental tradeoff between desirable high mobility and undesirable leakage current due to the small effective mass and bandgap. To understand leakage current limits in high-speed CNT transistors, electrical bandgaps are extracted on 12 single-CNT top-gate MOSFETs from the energy gap between thermion...

Emerging nonvolatile memory technologies are promising due to their anticipated capacity benefits, nonvolatility, and zero idle energy. One of the most promising candidates is resistive random access memory (RRAM) based on resistive switching (RS). This paper reviews the development of RS device technology including the fundamental physics, materia...

Large switching current density and resistance drift remain challenges for phase change memory (PCM) in data storage and neuromorphic computing applications. Here, we address these by electro-thermal and structural confinement in a GeTe/Sb2Te3 superlattice PCM (SL-PCM) with thermally-induced phase change, while observing scalability with bottom ele...

One of the major roadblocks for filamentary type resistive random access memory is variations in both the write voltage and the read resistance. The variation is inevitable because of the stochastic nature of oxygen ion movement inside the metal oxide. In this letter, we show that by inserting a thin SnO <sub xmlns:mml="http://www.w3.org/1998/Math/...

We present a DevIce-to-System Performance EvaLuation (DISPEL) workflow that integrates transistor and interconnect modeling, parasitic extraction, standard cell library characterization, logic synthesis, cell placement and routing, and timing analysis to evaluate system-level performance of new CMOS technologies. As the impact of parasitic resistan...

Learning from a few examples (one/few-shot learning) on the fly is a key challenge for on-device machine intelligence. We present the first chip-level demonstration of one-shot learning with Stanford Associative memory for Programmable, Integrated Edge iNtelligence via life-long learning and Search (SAPIENS), a resistive random access memory (RRAM)...

Flexing computer memory Phase change materials leverage changes in structure into differences in electrical resistance that are attractive for computer memory and processing applications. Khan et al . developed a flexible phase change memory device with layers of antimony telluride and germanium telluride deposited directly on a flexible polyimide...

Two-dimensional (2D) semiconductors have been proposed for heterogeneous integration with existing silicon technology; however, their chemical vapor deposition (CVD) growth temperatures are often too high. Here, we demonstrate direct CVD solid-source precursor synthesis of continuous monolayer (1L) MoS$_2$ films at 560 C in 50 min, within the 450-t...

Realizing today's cloud-level artificial intelligence functionalities directly on devices distributed at the edge of the internet calls for edge hardware capable of processing multiple modalities of sensory data (e.g. video, audio) at unprecedented energy-efficiency. AI hardware architectures today cannot meet the demand due to a fundamental "memor...

HfO₂-based resistive RAM (RRAM) is an emerging nonvolatile memory technology that has recently been shown capable of storing multiple bits-per-cell. The energy/delay costs of an RRAM write operation are dependent on the number of pulses required for RRAM programming. The pulse count is often large when existing programming approaches are used for m...

Two-dimensional (2D) semiconductors are promising candidates for scaled transistors because they are immune to mobility degradation at the monolayer limit. However, sub-10 nm scaling of 2D semiconductors, such as MoS2, is limited by the contact resistance. In this work, we show for the first time a statistical study of Au contacts to chemical vapor...

Learning from a few examples (one/few-shot learning) on the fly is a key challenge for on-device machine intelligence. We present the first chip-level demonstration of one-shot learning using a 2T-2R resistive RAM (RRAM) non-volatile associative memory (AM) as the backend of memory-augmented neural networks (MANNs). The 64-kbit fully integrated RRA...

We demonstrate single crystal growth of wafer-scale hexagonal boron nitride (hBN), an insulating atomic thin monolayer, on high-symmetry index surface plane Cu(111). The unidirectional epitaxial growth is guaranteed by large binding energy difference, ~0.23 eV, between A- and B-steps edges on Cu(111) docking with BN clusters, confirmed by density f...

The rapid growth and development of technology has had significant implications for healthcare, personalized medicine, and our understanding of biology. In this work, we leverage the miniaturization of electronics to realize the first demonstration of wireless detection and communication of an electronic device inside a cell. This is a significant...

Down‐scaling of transistor size in the lateral dimensions must be accompanied by a corresponding reduction in the channel thickness to ensure sufficient gate control to turn off the transistor. However, the carrier mobility of 3D bulk semiconductors degrades rapidly as the body thickness thins down due to more pronounced surface scattering. Two‐dim...

Hardware for deep neural network (DNN) inference often suffers from insufficient on-chip memory, thus requiring accesses to separate memory-only chips. Such off-chip memory accesses incur considerable costs in terms of energy and execution time. Fitting entire DNNs in on-chip memory is challenging due, in particular, to the physical size of the tec...

Increasing computation demand of machine learning (ML) applications (recommender system, image classification, speech recognition, and so on) calls for the development of specialized hardware for ML and neuromorphic computing. New memories, such as resistive random access memory (RRAM), can be used to store weights of neural networks and to acceler...

High switching current density has been a key bottleneck for phase change memory (PCM) technology. Here, we demonstrate interfacial thermoelectric heating (TEH) as a promising way of tackling this challenge. We use TEH induced by a thin Bi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Te <sub...

Self-Assembly, a process in which molecules, polymers, and particles are driven by local interactions to organize into patterns and functional structures, is being exploited in advancing silicon electronics and in emerging, unconventional electronics. Silicon electronics has relied on lithographic patterning of polymer resists at progressively smal...

The success of semiconductor electronics is built on the creation of compact, low-power switching elements that offer routing, logic, and memory functions. The availability of nanoscale optical switches could have a similarly transformative impact on the development of dynamic and programmable metasurfaces, optical neural networks, and quantum info...