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Low-power two-stage OP-AMP is presented here. The OP-AMP receives 0.9 V supply voltage with variation of 0.8–1 V. Designed OP-AMP was simulated in 16 nm CMOS technology (PTM—Predictive technology models) with variation in supply voltage and temperature. The overall gain of two-stage OP-AMP was found to be greater than 40 dB for 0–80 °C temperature...
Extremely low power, low voltage complete on-chip low drop-out voltage regulator (LDO) is presented. The LDO receives an unregulated supply of 0.5–1 V and regulates it to 0.4 V nominal output utilizing a 0.1 V on-chip reference voltage. A load capacitor of just 1pf is assumed to be present at LDO output. Designed voltage reference and complete LDO...
