Görschwin Fey

Görschwin Fey
Technische Universität Hamburg | TUHH

About

253
Publications
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1,747
Citations

Publications

Publications (253)
Preprint
Full-text available
Absolute position accuracy is the key performance criterion of an Indoor Localization System (ILS). Since ILS are heterogeneous and complex cyber-physical systems, the localization accuracy depends on various influences from the environment, system configuration, and the application processes. To determine the position accuracy of a system in a rep...
Preprint
Absolute position accuracy is the key performance criterion of an Indoor Localization System (ILS). Since ILS are heterogeneous and complex cyber-physical systems, the localization accuracy depends on various influences from the environment, system configuration, and the application processes. To determine the position accuracy of a system in a rep...
Preprint
There are numerous e-assessment systems devoted to specific domains under diverse license models. Cost, extensibility, and maintainability are relevant issues for an institution. Ease of use and inclusion into courses are educator's main concerns. For students the user experience and fast transparent feedback plus "better" tests are most important....
Chapter
Today’s systems are increasingly complex, often adaptable, and even autonomous. This makes designing, connecting, diagnosing, and using such systems difficult. Often this difficulty is due to a lack in understanding why a system acts as it does, i.e., why the system executes certain actions.
Article
Full-text available
Constructing good test cases is difficult and time-consuming, especially if the system under test is still under development and its exact behavior is not yet fixed. We propose a new approach to compute test strategies for reactive systems from a given temporal logic specification using formal methods. The computed strategies are guaranteed to reve...
Conference Paper
Full-text available
Several approaches exist for specification mining ofhardware designs, both at the RTL and system levels (e.g, TLM).These approaches mine assertions that specify the behavior ofthe design. Some of the techniques require the source codeitself while others can extract assertions directly from simulationtraces. The performance of some approaches is hig...
Conference Paper
Several approaches exist for specification mining of hardware designs, both at the RTL and system levels (e.g, TLM). These approaches mine assertions that specify the behavior of the design. Some of the techniques require the source code itself while others can extract assertions directly from simulation traces. The performance of some approaches i...
Preprint
Constructing good test cases is difficult and time-consuming, especially if the system under test is still under development and its exact behavior is not yet fixed. We propose a new approach to compute test strategies for reactive systems from a given temporal logic specification using formal methods. The computed strategies are guaranteed to reve...
Conference Paper
SpaceWire as a communication technology for serial data transfer is widely used in the space domain. Although the related ECSS standard describes how data routing in SpaceWire networks shall be implemented, the possibilities of applying real-time traffic are quite limited. As soon as more complex networks with cascades of routers are required, the...
Chapter
monitoring failures throughout the computing system
Article
Cyber-physical systems, that consist of a cyber part—a computing system—and a physical part—the system in the physical environment—as well as the respective interfaces between those parts, are omnipresent in our daily lives. The application in the physical environment drives the overall requirements that must be respected when designing the computi...
Article
Full-text available
Decision procedures are used as core tech-nique in many applications today. In this context, auto-mated reasoning based on Satisfiability Modulo Theories (SMT) is very effective. However, developers have to decide which concrete engine to use and how to integrate the engine into the application. Even if file formats like SMT-LIB standardize the inp...
Conference Paper
Fault injection and fault simulation are a typical approach to analyze the effect of a fault on a hardware/software system. Often fault injection is done on abstract models of the system either to retrieve early results when no implementation is available, yet, or to speed-up the runtime intensive fault simulation on detailed models. The simulation...
Conference Paper
Modern integrated circuits are often multi-core designs connected via communication elements like buses, bridges, and routers. Each of these communication elements requires a certain amount of time, called latency, for transferring data. When a system interacts cyber-physically with the real world via sensors and actuators guaranteeing that the com...
Conference Paper
Extended monitoring of housekeeping data is required to increase the observability of a spacecrafts health status, its environment and resulting mechanical stress as well as physical parameters like the spacecrafts position and orientation. This implies the application of an increasing number of onboard sensors for various physical quantities like...
Article
Full-text available
In space applications, the data logging sub-system often requires compression to cope with large amounts of data as well as with limited storage and communication capabilities. The usage of Commercial off-the-Shelf (COTS) hardware components is becoming more common, since they are particularly suitable to meet high performance requirements and also...
Conference Paper
We present a technique to automatically generate SystemVerilog-Assertions from designs using dynamic dependency graphs. We extract relations between signals of the design using only a few simulation runs, which drastically reduces the required number of use cases compared to other approaches. Additionally, unlike previous approaches, we do not use...
Conference Paper
The Exists-Forall (EF) synthesis problem deals with finding parameters such that for all input assignments a correctness specification is met. Many standard problems from computer-aided design and verification can be formulated as an instance of EF synthesis when a function template with holes — parameters to be synthesized — is provided. In this p...
Conference Paper
We present an outline of the field of Multilevel Design Understanding by first defining and motivating the related problems, and then describing the key issues which must be addressed in future research.
Conference Paper
We propose an exact algorithm to model-free diagnosis with an application to fault localization in digital circuits. We assume that a faulty circuit and a correctness specification, e.g., in terms of an un-optimized reference circuit, are available. Our algorithm computes the exact set of all minimal diagnoses up to cardinality k considering all po...
Article
Debugging is a time consuming task in hardware design. In this paper a new debugging approach based on the analysis of dynamic dependency graphs is presented. Powerful techniques for software debugging, including reverse debugging, dynamic forward and backward slicing, and spectrum-based fault localization are combined and adapted for hardware desi...
Article
Local triple modular redundancy (LTMR) is often the first choice to harden the FFs of a flash-based FPGA application against radiation-induced bitflips in space, but LTMR leads to an area overhead of roughly 300%. To cope with this significant overhead, we propose an error detection based approach. In this work, we compare parity-based error detect...
Chapter
Datenspeicher in Raumfahrtanwendungen sind ein wichtiger Teil des gesamten Systems. Die typischerweise verbauten Speicherchips sind durch ihre hohe Robustheit und besondere Fertigungsgüte sehr teuer. Es ist sinnvoll, stattdessen günstigen aber fehleranfälligen NAND-Flash zu benutzen und ihn durch eine vom Dateisystem gesteuerte Redundanz sicherer z...
Conference Paper
We propose an approach for overapproximating the Worst-Case Execution Time (WCET) of embedded control software using formal methods. Model checking is iteratively applied to compute the WCET from the machine code of the software considering a platform and an environment model. We implemented the approach and present first experiments for a thermal...
Conference Paper
With decreasing size of transistors, the impact oftransient faults as well as the local and global variability of transistors increases, affecting system functions and performances. Formal verification may be used to prove that a circuit isrobust against transient and parametric faults. However, a modelincluding timing information combined with ext...
Conference Paper
In this paper, we propose a counterexample-guided diagnosis approach to identify faults in circuit designs described as net-lists on the gate-level. Given a faulty net-list and a logic specification of the correct, intended behavior of the circuit, the diagnosis algorithm iteratively computes the exact set of fault candidates, i.e., a subset of the...
Conference Paper
As systems become more complex, the size of transistors decreases. This effect leads to an increased probability of transient faults as well as higher variability of the transistors. Verifying that circuits are robust against transient faults and variability is mandatory. While formal verification may be used to prove robustness, a model that inclu...
Conference Paper
Local triple modular redundancy (LTMR) is often the first choice to harden a flash-based FPGA application against soft errors in space. Unfortunately, LTMR leads to at least 300% area overhead. We propose a parity-based error detection approach, to use the limited resources of space-proven flash-based FPGAs more area-efficiently; this method can be...
Conference Paper
Data logging applications, such as those deployed in satellite launchers to acquire telemetry data, may require compression algorithms to cope with large amounts of data as well as limited storage and communication capabilities. When commercial-off-the-shelf hardware components are used to implement such applications, radiation-induced soft errors...
Article
OBC-NG is the abbreviation for on-board-computer next generation – a project founded and made by the German Aerospace Center (DLR). The project goal is to provide the basis for future on-board computer (OBC) for space-missions. This document summarizes the conducted work, made in the DLR-project OBC-NG and its predecessor project “Software and Hard...
Conference Paper
Nowadays, before a microchip’s concrete implementation is available a more abstract model, e.g., on electronic System level (ESL) is created. To ensure a better design understanding a matching of both model’s variables is proposed. But how to map a variable from the abstract model to a variable form the concrete model? We evaluate a simulation base...
Conference Paper
The final design of today’s ICs is in many cases created by combining functional blocks from various vendors or reusing them from previous projects. Often only partial information about the internal behavior of such blocks is available. One way to describe the behavior of a functional block are formal properties. The advantage of properties in comp...
Conference Paper
We present a simple, yet flexible parameter synthesis and repair approach for Cyber-Physical Systems (CPS). The user defines the behavior of a CPS, a set of (un)safe states, and a generic template for an inductive invariant using Satisfiability Modulo Theories (SMT) formulas. Counterexample-Guided Inductive Synthesis (CEGIS) is then used to compute...
Chapter
Design bugs at RTL are classified into three major classes: logic bugs, algorithmic bugs and synchronization bugs [CMA08]. There is a range of approaches to automate the debugging process for logic bugs [SVAV05, CMB07b, SFD10, SFB+09]. Algorithmic bugs often have a severe impact on the correctness of a design. Multiple major modifications are usual...
Chapter
Variability is recognized to be a major challenge in analyzing the circuits as IC technology continues to scale down. In this case, delay deviations are imposed by process variations such as uncertainty in the parameters of fabricated devices and interconnects, and by environmental variations such as temperature and voltage [BCSS08, APP10, SGT+08].
Chapter
This chapter deals with the automation of post-silicon debugging for speed-limiting paths, briefly called speedpaths. Debugging of speedpaths is a key challenge in development of VLSI circuits as timing variations induced by process and environmental effects are increasing.
Chapter
The cost of VLSI systems verification and debugging has significantly grown in the recent years as design size and complexity have increased. Also due to time-to-market constraints, 100 % verification coverage at the design level is an elusive task. Consequently, automated debugging approaches are required at both pre-silicon and post-silicon stage...
Chapter
FPGAs are often utilized in space avionics. To protect the FPGA application data against radiation effects in space, data redundancy can be used. A well-known method is to triplicate the circuit and eliminate the erroneous circuit output with a local voter (TMR). Alternatively, in-circuit error detection with software-based error correction can be...
Chapter
Due to the decreasing size of transistors, the probability of transient errors and the variability of the transistor’s characteristics in electrical circuits are continuously increasing. These issues demand for techniques to check the robustness of circuits and their behavior under transient faults and variability. Furthermore, the implementation o...
Article
Various problems from artificial intelligence and formal methods are solved utilizing Satisfiability Modulo The-ories (SMT) solvers. Selecting the best SMT solver for a specific application, however, is a daunting task. In this paper, we present the novel metaSMT TCP server and client architecture which can be used to solve SMT instances expressed...
Article
The complexity of modern chip designs is rapidly increasing. More and more blocks from old designs are reused and third party IP is licensed to fulfill strict time-to-market constraints. Often, poor documentation of such blocks makes improvements and extensions of the blocks a difficult time consuming task. In this paper we present a technique for...
Article
Full-text available
We propose a path-based approach to program repair for imperative programs. Our repair framework takes as input a faulty program, a logic specification that is refuted, and a hint where the fault may be located. An iterative abstraction refinement loop is then used to repair the program: in each iteration, the faulty program part is re-synthesized...
Article
Due to timing variations induced by process variations and environmental effects, speedpath debugging becomes a major concern in the design of high performance VLSI circuits. In this paper, we propose an efficient approach to speedpath debugging based on Boolean Satisfiability (SAT). We use a time-discrete model of the circuit for analyzing effects...
Book
This book describes automated debugging approaches for the bugs and the faults which appear in different abstraction levels of a hardware system. The authors employ a transaction-based debug approach to systems at the transaction-level, asserting the correct relation of transactions. The automated debug approach for design bugs finds the potential...
Conference Paper
Due to the decreasing size of transistors, the probability of transient errors and the variability of the transistor’s characteristics in electrical circuits continues increasing. These issues demand for techniques to check the robustness of circuits and their behavior under transient errors and conservative variability approximations. We present a...
Chapter
Automated debugging approaches are necessary to speed up the design process as size and complexity of VLSI designs increase. Among these approaches, debugging based on SAT [SVAV05] has been shown as a robust and efficient approach. The purpose of SAT-based debugging is to identify the potential sources of an observed error by using the available co...
Chapter
Each combinational circuit is represented by a directed acyclic graph C = (V, E), referred to as the circuit graph, where V is the set of circuit nodes and E ⊆ V × V, the set of edges, corresponds to the gate input-output connections in the circuit [LRS89]. For gate-level benchmarks, we consider the nodes to be gates with symmetric functions. Each...
Article
The complexity of modern chips is rapidly increasing. To fulfill tight time-to-market constraints, more and more blocks from previous designs are reused or third party IP blocks are licensed. However, such blocks are often only poorly documented making adjustments to the blocks a difficult task. This paper presents a technique for automatic feature...
Conference Paper
Verification of complex networks, especially meshed networks created of routers, can become quite difficult. There are several parameters influencing the actual data throughput, e.g., congestion in the network, transmission rates at the inputs of the network or between routers as well as the reception rate of data. An appropriate model is required...
Article
Facing a wide range of mission requirements and the integration of diverse payloads requires extreme flexibility in the on-board-computing infrastructure for scientific missions. We show that scalability is principally difficult. We address this issue by proposing a base level design and show how the adoption to different needs is achieved. Inter-d...
Conference Paper
A major concern in the design of high performance VLSI circuits is speedpath debugging. This is due to the fact that timing variations induced by process variations and environmental effects are increasing as the size of VLSI circuits is shrinking. In this paper, a speedpath debugging approach based on Boolean Satisfiability (SAT) is proposed. The...
Conference Paper
In modern chip design, many different blocks are assembled in a single chip. Normally, these blocks have been written by different developers or even licensed from other companies. Correctly connecting all blocks is a tedious task. State of the art tools for automatically generating the connections either require identical port-names or additional...
Article
Verifying correctness is a major bottleneck in today’s circuit and system design. Verification includes the tasks of error detection, error localization, and error correction in an implemented design, as well as the analysis and avoidance of transient faults. For all those tasks, knowing when an assignment to signals becomes observable at the outpu...
Conference Paper
The computational demands on spacecraft are rapidly increasing. Current on-board computing components and architectures cannot keep up with the growing requirements. Only a small selection of space-qualified processors and FPGAs are available and current architectures stick with the inflexible cold-redundant structure. The objective of the ongoing...
Conference Paper
As complexity and size of Systems-on-Chip (SoC) grow, debugging becomes a bottleneck for designing IC products. In this paper, we present an approach for online debug of NoC- based multiprocessor SoCs. Our approach utilizes monitors and filters implemented in hardware. Monitors and filters observe and filter transactions at run-time. They are conne...
Book
Eingebettete Systeme übernehmen zentrale Steueraufgaben im täglichen Leben. In der Energieversorgung oder im Transportwesen würde ein Ausfall der Systeme fatale Auswirkungen haben. Der Nutzer verlässt sich aber auf ein fehlerfreies Funktionieren des Systems. Die Funktionstüchtigkeit der Schaltkreise zu garantieren, ist das Ziel des Testens – und da...
Conference Paper
One major concern in the design of Very-Large- Scale Integrated (VLSI) circuits is debugging as design size and complexity increase. Automation of the debugging process helps to decrease the development cycle of VLSI circuits and consequently to achieve a higher productivity. This paper presents an approach to automatically debug synchronization bu...
Conference Paper
Various problems from artificial intelligence and formal methods are solved utilizing Satisfiability Modulo The- ories (SMT) solvers. Selecting the best SMT solver for a specific application, however, is a daunting task. In this paper, we present the novel metaSMT TCP server and client architecture which can be used to solve SMT instances expressed...
Conference Paper
The complexity of modern chip designs is rapidly increasing. More and more blocks from old designs are reused and third party IP is licensed to fulfill strict time-to-market constraints. Often, poor documentation of such blocks makes improvements and extensions of the blocks a difficult time consuming task. In this paper we present a technique for...
Article
This paper presents a novel approach to automate speedpath debugging taking into account variations. The proposed technique is based on Boolean Satisfiability (SAT) and the approach is based on converting the timing behavior of a circuit into the functional domain, inserting a variation logic into the model, and using a Boolean Satisfiability solve...
Conference Paper
Speedpath diagnosis is one of the major challenges in designing high-performance Very-Large-Scale Integrated (VLSI) circuits due to timing variations caused by process variations and environmental effects. In this paper, an efficient approach to automate speedpath debugging is presented. The approach relies on converting the timing behavior of a ci...
Conference Paper
The increasing complexity of circuits and systems is forcing design specifications to software-like programming languages like C. Since the conversion from software to hardware is a difficult task solved manually, bugs are frequently introduced in the HDL design. Sophisticated automated error localization and correction techniques, i.e. debugging,...
Conference Paper
Full-text available
We cordially welcome all participants of DDECS 2013 to Karlovy Vary - the most famous spa town of the Czech Republic. The DDECS symposium series has been organized by the Czech Republic (1997, 2002, 2006, 2009), Poland (1998, 2003, 2007), Slovakia (2000, 2004, 2008), Hungary (2001, 2005), Austria (2010), Germany (2011) and Estonia (2012). After our...