Gaurav Narang

Indraprastha Institute of Information Technology | IIITD · VLSI and Embedded systems

Embedded memories are the key contributor to the chip area, dynamic power dissipation and also form a significant part of critical path for high performance advanced SoCs. Therefore, optimal selection of memory instances becomes imperative for SoC designers. While EDA tools have evolved over the past years to optimally select standard logic cells d...

SRAMs occupy more than 50% of die area in high performance SoCs. Device variations in advanced technology nodes limit SRAM cell performance and yield. Maximum write time defines performance limited yield for SRAMs. In this work, we estimate sensitivity of write time of a 6T SRAM cell to variations in different devices through Design of Experiments...