Frederick T Chen

• PhD, Cornell University
• Winbond Electronics

Resistance-switching devices such as resistive random access memories (RRAMs) exhibit the ability to rapidly reduce resistance upon exceeding a threshold voltage, as part of the SET operation. For oxide-based RRAMs, the progressive generation of defects during SET requires strict regulation of the current, e.g., by a transistor, in order to avoid i...

Three-dimensional resistive random access memory (3D-RRAM) potentially offers lowest cost per bit and highest bit density memory architecture without the use of transistors in the array. However, without the use of selectors attached to each cell in the array, sneak currents are a key concern, causing signal errors and excess power dissipation. A n...

Resistive random access memory (RRAM) is a promising new non-volatile memory technology capable of operating at low power as well as high speed. Although RRAM is capable of lower energy consumption and substantially more cycles than Flash memory, comprehending and maintaining its ability to store data under stressed conditions remains the key chall...

Consumer gadgets make up the fastest growing market for electronic devices today. These products will rely more and more on embedded storage-type memory, which can store system and processing data without impacting standby power consumption. For embedded memory applications, including microcontrollers, automotive, and mobile code storage applicatio...

A novel line-offset detector array (LODA) is demonstrated for the first time, which can resolve projected patterns in extreme ultraviolet (EUV) scanners for advanced integrated circuit (IC) processes. Fine layout patterns on the projected plane can be truthfully reconstructed by the uniquely designed line-offset array. With nano-meter spatial resol...

This study proposes a synthesis strategy of high‐quality graphene films on the copper foil at a temperature of 400 °C throughout the graphene growth process without employing high‐temperature annealing. Through continuous CO2 laser pretreatment of the copper foil, the surface smoothness improves, and the removal of copper particles and copper oxide...

This study introduces a breakthrough achievement of 0.1-Gb/mm $^{\text{2}}$ wing-shaped high-density embedded 3-D via resistive random access memory (Via RRAM) in TSMC’s 16-nm FinFET CMOS logic process. The 3-D Via RRAM cell is vertically structured as a 1T10R configuration; these ten switchable resistive unit cells stacked across five copper laye...

An on-wafer 3-D electron beam (e-beam) detector cube for in situ monitoring of advanced lithography processes is presented. The proposed detector array stands out because of its full compatibility with the FinFET CMOS logic process, heightened sensing resolution, and capability for battery-less sensing. The in situ stored sensed signal is accessibl...

A novel 3D stackable Via resistive random access memory (RRAM) latch and Via RRAM logic gates implemented in 16-nm FinFET logic process for computing-in-memory (CIM) applications are proposed. Via RRAM latch array can provide more than 60 Mb/mm2 of latch storage density to achieve stable full-swing high-speed output. By simplifying the readout circ...

In this work, multi-level storage in the via RRAM has been first time reported and demonstrated with the standard FinFET CMOS logic process. Multi-level states in via RRAM are achieved by controlling the current compliance during set operations. The new current compliance setting circuits are proposed to ensure stable resistance control when one co...

Owing to the increasing demand for monitoring harmful toxic gases using small‐sized low‐power‐consumption gas sensors, a room‐temperature wireless complimentary gas sensor incorporating layered materials is proposed and demonstrated. The compact design allows the sensing module to be installed under all conditions and facilitates multiple detection...

The research showcases innovative embedded artificial synaptic devices (eASDs) implemented in a CMOS logic platform. These eASD devices demonstrate a large sensing window, exceptional endurance, and reliable data retention. Moreover, they can seamlessly integrate into neural network (NN) circuits, effectively functioning as synapses with adjustable...

In this study, a novel self-rectifying twin-bit Via Resistive random-access memory (Via RRAM) has been implemented in a cross-bar memory array using via and metal layers within the standard FinFET Back End of Line processes (BEOL). By using SiOx and TaOx, this RRAM integrates well with advanced CMOS logic circuits. Additionally, this device can be...

A top‐down transfer process is developed via a rolling process associated with thermal release tape/poly(methyl methacrylate) (PMMA) bi‐supporting layers to realize large‐scale transfer processes on transition metal dichalcogenide materials. A 2‐inch MoS 2 thin film transferred on SiO 2 /Si substrates with high integrity and a yield of ≈99% can be...

The previous work proposed a 1-transistor-2-bit (1T2B) offset via antifuse memory implemented by FinFET CMOS logic processes. Through the self-aligned via process, spacing between via and metal can form a via-dielectric-metal structure, which can switch between states by forming a conductive path bridging the electrodes. In this 1T2B cell, multilev...

This research presents an innovative gas sensor system featuring a selenized 2D-film as its primary sensing material, integrated with metal-gate-coupled floating gate devices to enable self-convergent calibration. The inherent variability in resistance levels of 2D gas-sensing materials across different devices has been a significant challenge, res...

A 4K detector array for on-wafer extreme ultraviolet (EUV) imaging is first-time demonstrated. The proposed detector array features full FinFET CMOS logic compatibility, compact 1T pixel, high spatial resolution, and battery-less sensing. The in situ stored sensed signal can be accessed through offline nondestructive wafer-level tests. EUV images p...

A novel 2-transistor (2T) pixel EUV detector is proposed and demonstrated by advanced CMOS technology. The proposed 2T detector also exhibits high spectral range (< 267 nm) and spatial resolution (67 μm) with high stability and CMOS Compatibility. The compact 2T EUV detector pixels arranged in a test array are capable of on-wafer recording the 2D E...

In this study, a multilevel logic-compatible two-transistor-two-resistor (2T2R) latch array for computing-in-memory (CIM) is proposed, featuring high power efficiency, fast response, and high resolution. Combining the resistive switching pairs of the Hf-based gate dielectric layers and a near-threshold-operated output transistor for resistance rati...

In the extreme ultraviolet lithography system, EUV-induced hydrogen plasma charging effect is observed by in situ embedded micro-detector array. The 4k-pixel on-wafer array can detect and store the distributions of H2 plasma in each in-pixel floating gate for non-destructive off-line read. The local uniformity of H2 plasma intensity extracted by th...

An on-wafer micro-detector for in situ EUV (wavelength of 13.5 nm) detection featuring FinFET CMOS compatibility, 1 T pixel and battery-less sensing is demonstrated. Moreover, the detection results can be written in the in-pixel storage node for days, enabling off-line and non-destructive reading. The high spatial resolution micro-detectors can be...

This work demonstrates a newly designed metal-gate coupled recorder for evaluating the plasma charging effect in fin-shaped field-effect transistor (FinFET) back-end-of-line (BEOL) processing steps. With more precise readings, the modified recorders are arranged in an array to further study the charging polarity and patterning effects during plasma...

A 2D SnSe2 layered film-based gas detector incorporating a floating-gate device coupled with metal interconnect wiring structures is proposed and demonstrated for the first time. Linear amplification can be readily implemented using a coupling ratio design, which refers to the capacitance ratio between the gate and device in the sense amplifier cir...

A novel in situ imaging solution and detectors array for the focused electron beam (e-beam) are the first time proposed and demonstrated. The proposed in-tool, on-wafer e-beam detectors array features full FinFET CMOS logic compatibility, compact 2 T pixel structure, fast response, high responsivity, and wide dynamic range. The e-beam imaging patte...

This work proposed a modified plasma induced charging (PID) detector to widen the detection range, for monitoring the possible plasma damage across a wafer during advanced CMOS BEOL processes. New antenna designs for plasma induced damage patterns with extended capacitors are investigated. By adapting the novel PID detectors, the maximum charging l...

A multifunctional ion‐sensitive floating gate Fin field‐effect transistor (ISFGFinFET) for hydrogen and sodium detection is demonstrated. The ISFGFinFET comprises a FGFET and a sensing film, both of which are used to detect and improve sensitivity. The sensitivity of the ISFGFinFET can be adjusted by modulating the coupling effect of the FG. A nano...

An in-tool, on-wafer detectors’ array for monitoring deep ultraviolet (DUV) light is proposed and demonstrated in this work. The proposed electronic layer detectors array (ELDA) features FinFET CMOS compatibility and compact pixel structure. Its minimum pixel pitch can reach 0.7 $\mu \text{m}$ , enabling the realization of high spatial resolution...

As one of the most promising embedded non-volatile storage solutions for advanced CMOS modules, resistive random access memory’s (RRAM) applications depend highly on its cyclability. Through detailed analysis, links have been found between noise types, filament configurations and the occurrence of reset failure during cycling test. In addition, a r...

A novel electron beam detector made on Si wafers by the advanced CMOS FinFET processes has been proposed in this study. Through electron beam (e-Beam) charging of on-wafer sensing pads, electron dosage can be registered on the detector for follow-up read-out. Without external power or battery connections, this detector has successfully delivered on...

This work proposed a modified plasma induced charging recorder to widen detection range, for monitoring the possible plasma damage across a wafer during advanced CMOS BEOL processes. New antenna designs for plasma induced damage patterns with extended capacitance are investigated. By adapting the novel PID recorders, maximum charging levels of the...

High-density interconnects, enabled by advanced CMOS Cu BEOL technologies, lead to closely placed metals layers. High-aspect ratio metal lines require extensive plasma etching processes, which may cause reliability concerns on inter metal dielectric (IMD) layers. This study presents newly proposed test patterns for evaluating the effect of plasma-i...

The main challenge in ferroelectric (FE) random access memory (FRAM) scaling is to maintain a high polarization density on the vertical sidewall of 3-D FE capacitors. Two simple and effective methods—stress engineering and optimized interface orientation—are proposed to facilitate the preferential transition from the tetragonal to the orthorhombic...

A new self-converging programming characteristic in a single-poly floating-gate memory cell with full-compatibility to a CMOS logic technology is observed and studied. A uniquely design cell with a narrow-bridging line between two coupling capacitors promotes a localized charging effect at the electron tunneling site, leading to clamping of thresho...

In this article, a single-layer complementary latch (CL) and one multilayer CL which are fully compatible with standard FinFET CMOS processes are characterized and their applications are extensively discussed. Through the complementary pair with the 3-D stackable twin-bit resistive random-access memory (RRAM) which consists of a TaON-based resistiv...

A novel microdetector array (MDA) for monitoring electron beam (eBeam) and extreme ultraviolet (EUV) lithography processes in 5 nm and beyond FinFET technology is first-time presented. This on-wafer detector array consists of high-density sensing cells which are fully compatible with standard FinFET CMOS processes. Fin coupling structures and energ...

Fast and stable switching between states is one of the key factors for the success resistive random access memory (RRAM) development. In an array, wide reset efficiency variation in RRAM cells is found to link to the characteristics of its low frequency noise (LFN) in bit-cell current. Through Monte Carlo simulation on randomly placing conductive f...

Computing-in-memory (CIM) based on embedded nonvolatile memory is a promising candidate for energy-efficient multiply-and-accumulate (MAC) operations in artificial intelligence (AI) edge devices. However, circuit design for NVM-based CIM (nvCIM) imposes a number of challenges, including an arealatency-energy tradeoff for multibit MAC operations, pa...

Non-volatile computing-in-memory (nvCIM) could improve the energy efficiency of edge devices for artificial intelligence applications. The basic functionality of nvCIM has recently been demonstrated using small-capacity memristor crossbar arrays combined with peripheral readout circuits made from discrete components. However, the advantages of the...

In this paper, a novel 4T-2R self-aligned nitride (SAN) cell-integrated static random-access memory (SRAM) cell is first implemented for true random number generator (TRNG) applications. The SRAM can be latched to either state by the unpredictable random telegraph noise (RTN) on the contact RRAMs (CRRAMs). With a self-convergent trimming mechanism,...

A novel plasma Charge Accumulative Model (pCAM) by calculating time-integrated Fowler-Nordheim (FN) tunneling charges and field of the gate dielectric in plasma processes is proposed in this paper. Our prior studies have developed and presented a quantitative FinFET plasma recording device by an effective fin-shaped field effect transistor (FinFET)...

In this work, we present a novel pH sensor using efficient laterally coupled structure enabled by Complementary Metal-Oxide Semiconductor (CMOS) Fin Field-Effect Transistor (FinFET) processes. This new sensor features adjustable sensitivity, wide sensing range, multi-pad sensing capability and compatibility to advanced CMOS technologies. With a sel...

Many cost-aware IoE devices require embedded nonvolatile memory (eNVM) to achieve high-speed read and low-power write operations for serving as code and data storage unit. Resistive random access memory (ReRAM) is a good candidate for eNVM of Internet-of-Everything (IoE) but suffers low read yield and require long read latency (T <sub xmlns:mml="ht...

A series FinFET based non-volatile logic gates with multiple logic functions defined by embedded non-volatile states are proposed for the first time and demonstrated in advanced CMOS technology platform. The device channels in the proposed CMOS logic gate is controlled by a metal floating gate coupled by slot contacts uniquely available in the FinF...

Near-infrared (NIR) sensors has become one of the key components in applications such as temperature, proximity, and even fingerprint sensing. A novel full-CMOS (Complementary Metal-Oxide-Semiconductor) compatible near-infrared sensor is proposed and demonstrated in this article. This sensing device consists of a gateless transistor, enabling near-...

Plasma induced damage remains a critical concern in VLSI manufacturing process as a result of the introduction of the high-k and low-k dielectric layers and complicated 3D structures in advanced technology nodes. In this study, the level of plasma induced charging distribution on a wafer is studied comprehensively. A strong correlation between the...

A via resistive random access memory (RRAM) cell fully compatible with the standard CMOS logic process has been successfully demonstrated for high-density logic nonvolatile memory (NVM) modules in advanced FinFET circuits. In this new cell, the transition metal layers are formed on both sides of a via, given two storage bits per via. In addition to...

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents po...

A novel device for monitoring plasma-induced damage in the back-end-of-line (BEOL) process with charge splitting capability is first-time proposed and demonstrated. This novel charge splitting in situ recorder (CSIR) can independently trace the amount and polarity of plasma charging effects during the manufacturing process of advanced fin field-eff...

Correction: In the original publication [1] Fig. 3 was presented incorrect. The correct additional file has been included with this erratum and the original article has been updated to rectify this error.

With an ever-increasing demand for energy efficiency, processors with instant-on and zero leakage features are highly appreciated in energy harvesting as well as "normally off" applications. Recently, zero-standby power and fast switching nonvolatile processors (NVPs) have been proposed based on emerging nonvolatile memories (NVMs), such as ferroel...

Nonvolatile flip-flops (nvFFs) enable frequent-off processors to achieve fast power-off and wake-up time while maintaining critical local computing states through parallel data movement between volatile FFs and local nonvolatile memory (NVM) devices. However, current nvFFs face challenges in large store energy (ES) and long voltage stress time on t...

This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application. With compact cell area and full logic compatibility, this new nv-SRAM incorporates two STI-ReRAMs embedded inside the 4T SRAM. Data can be read/write...

In this paper, we present a new differential multiple-time-programmable (MTP) memory cell with a novel slot contact coupling structure in the fin field-effect transistor (FinFET) CMOS process. This MTP cell contains a pair of floating metal gates to store differential data on a single cell. Through differential read operations, the cells are less s...

A full logic-compatible embedded gate contact resistive random access memory (GC-RRAM) cell in the CMOS FinFET logic process without extra mask or processing steps has been successfully demonstrated for high-density and low-cost logic nonvolatile memory (NVM) applications. This novel GC-RRAM cell is composed of a transition metal oxide from the gat...

A thorough investigation of the parasitic resistance and capacitance (RC) effects of a single-fin FinFET on logic CMOS devices and circuits is presented. As parasitic RC effects become increasingly prominent in nanoscaled FinFET technologies, they are critical to the overall device and circuit performance. In addition, the effects of dummy patterns...

Recent nonvolatile flip-flops (nvFFs) enable the parallel movement of data locally between flip-flops (FFs) and nonvolatile memory (NVM) devices for faster system power off/on operations. The wide distribution and long period in NVM-write times of previous two-NVM-based nvFFs result in excessive store energy (Es) and over-write induced reliability...

A full logic compatible 4T2R nonvolatile Static Random Access Memory (nv-SRAM) is successfully demonstrated in pure 40nm CMOS logic process. This non-volatile SRAM consists of two STI RRAMs embedded inside the 4T SRAM with minimal area penalty and full logic compatibility. Data is accessed through SRAM cells, and stored by switching one of the load...

A new two-transistor logic resistive random-access memory (RRAM) cell with a 16-nm standard FinFET CMOS logic platform that is fully compatible with the CMOS process is proposed and demonstrated in a 1-kb FinFET dielectric RRAM (FIND RRAM) array. The new 16-nm FIND RRAM comprises two logic standard FinFET transistors with a HfO₂-based composite res...

A contact resistive random access memory (RRAM) cell consisting of a W/TiON/SiO2/N⁺ silicon film stack realized using a new contact backfilled process is investigated. To precisely control RRAM film thicknesses on contact RRAM devices, in this paper, a new backfilling process of SiO2 deposition after contact etching via plasma-enhanced chemical vap...

A new operation scheme is proposed for achieving multilevel storage in FinFET one-time programmable (OTP) cells by a high-κ metal gate CMOS process. The OTP cells are programmed by breaking down the gate dielectric layer, during which the corner effect in the FinFET structure shortens the program time and lowers the program voltages. The after-brea...

In this letter, a new ultrahigh-density memory constructed with a contact resistive random access memory (RRAM) is proposed. This slot contact RRAM (SCRRAM) with transition metal oxide from contact liner layers has been successfully demonstrated by a standard 16-nm FinFET process without extra mask or processing step. The new FinFET RRAM features l...

A fully CMOS compatible one-time programmable (OTP) cell with a novel intra-fin cell isolation (IFCI) structure on a FinFET CMOS process has been proposed. The IFCI OTP cell utilizes the field-enhanced dielectric breakdown at fin corners to perform a fast and low-voltage program operation. Moreover, an ultrasmall intra-fin cell-to-cell isolation is...

A thorough analysis of the FinFET resistance and current distribution is presented. By combining multiple conventional and novel measurement techniques, the key components that contribute to the parasitic resistance of FinFETs can be quantified. Through a three-dimensional (3D) FinFET resistance network model, the impact of the FinFET 3D structure...