Francesca Palumbo

Università degli Studi di Sassari | UNISS

Multithreading is a well-known technique for general-purpose systems to deliver a substantial performance gain, raising resource efficiency by exploiting underutilization periods. With the increase of specialized hardware, resource efficiency became fundamental to master the introduced overhead of such kind of devices. In this work, we propose a mo...

Cite as: Author/s, “Title of contribution-presentation”, in Proceedings of the 3rd Summer School on Cyber-Physical Systems and Internet-of Things, Editors: Lech Jozwiak, Radovan Stojanovic and Nikolaos Voros, Vol. III, June 2022, pp. xx-yy, DOI: https://doi.org/10.5281/zenodo.6698644 Citation example: Lech Jóźwiak, Green CPS and IoT for Green Wo...

In embedded and cyber-physical systems, the design of a desired functionality under constraints increasingly requires parallel execution of a set of tasks on a heterogeneous architecture. The nature of such parallel systems complicates the process of understanding and predicting performance in terms of response time. Indeed, response time depends o...

Cyber-Physical Systems (CPSs) are dynamic and reactive systems interacting with processes, environment and, sometimes, humans. They are often distributed with sensors and actuators, characterized for being smart, adaptive, predictive and react in real-time. Indeed, image- and video-processing pipelines are a prime source for environmental informati...

Advanced computations on embedded devices are nowadays a must in any application field. Often, to cope with such a need, embedded systems designers leverage on complex heterogeneous reconfigurable platforms that offer high performance, thanks to the possibility of specializing/customizing some computing elements on board, and are usually flexible e...

An early estimation of the exact number of fruits, flowers, and trees helps farmers to make better decisions on cultivation practices, plant disease prevention, and the size of harvest labor force. The current practice of yield estimation based on manual counting of fruits or flowers by workers is a time consuming and expensive process and it is no...

The Chapter begins with a discussion of the constraints and needs of video coding systems. The lack in flexibility of traditional monolithic codec specifications, not suitable to model commonalities among codecs and foster reusability among successive codec generations/updates, was the main trigger for the development of a new standard initiative w...

Modern embedded and cyber-physical systems require every day more performance, power efficiency and flexibility, to execute several profiles and functionalities targeting the ever growing adaptivity needs and preserving execution efficiency. Such requirements pushed designers towards the adoption of heterogeneous and reconfigurable substrates, whic...

In the era of Cyber Physical Systems, designers need to offer support for run-time adaptivity considering different constraints, including the internal status of the system. This work presents a run-time monitoring approach, based on the Performance Application Programming Interface, that offers a unified interface to transparently access both the...

Understanding and predicting response time is a major concern in most systems. However, the complexity of heterogeneous Multiprocessor Systems-on-Chipss (MPSoCss) makes it difficult to provide early evaluation of system execution latency when executing parallel applications. In particular, knowledge about the factors that determine latency is a mus...

Modern embedded and cyber-physical systems require every day more performance, power efficiency and flexibility, to execute several profiles and functionalities targeting the ever growing adaptivity needs and preserving execution efficiency. Such requirements pushed designers towards the adoption of heterogeneous and reconfigurable substrates, whic...

Cyber-Physical Systems (CPS) are dynamic and reactive systems interacting with processes, environment and, sometimes, humans. They are often distributed with sensors and actuators, smart, adaptive, predictive and react in real-time. Indeed, as sight for human beings, image- and video-processing pipelines are a prime source for environmental informa...

In this paper, we present a new, simple, accurate and fast power estimation technique that can be used to explore the power consumption of digital system designs at an early design stage. We exploit the machine learning techniques to aid the designers in exploring the design space of possible architectural solutions, and more specifically, their dy...

Modern embedded computing platforms used within Cyber-Physical Systems (CPS) are nowadays leveraging more and more often on heterogeneous computing substrates, such as newest Field Programmable Gate Array (FPGA) devices. Compared to general purpose platforms, which have a fixed datapath, FPGAs provide designers the possibility of customizing part o...

Computer aided design is nowadays a must to quickly provide optimized circuits, to cope with stringent time to market constraints, and to be able to guarantee colliding constrained requirements. Design automation is exploited, whenever possible, to speed up the design process and relieve the developers from error prone customization, optimization a...

This paper describes the activities related to the implementation of a robotic arm controller based on the Damped Least Square algorithm to numerically solve Inverse Kinematics problems over a heterogeneous MPSoC platform.

Cyber-Physical Systems (CPS) are interconnected devices, reactive and dynamic to sensed external and internal triggers. The H2020 CERBERO EU Project is developing a design environment composed by modelling, deployment and verification tools for adaptive CPS. This paper focuses on its efficient support for run-time self-adaptivity.

INTRODUCTION:: Cyber comes from Greek adjective kyberneticos (cybernetic) which means skilled in steering or governing. Already from ancient times people constructed various machines (physical systems) and their controllers (cyber systems). Cyber-physical system (CPS) is a compound system engineered through integration of cyber and physical sub-s...

In this paper, we present a flexible, simple and accurate power modeling technique that can be used to estimate the power consumption of modern technology devices. We exploit Artificial Neural Networks for power and behavioral estimation in Application Specific Integrated Circuits. Our method, called NeuPow, relies on propagating the predictors bet...

Cyber-Physical Systems (CPS) are systems that are in feedback with their environment, possibly with humans in the loop. They are often distributed with sensors and actuators, smart, adaptive and predictive and react in real-time. Image- and video-processing pipelines are a prime source for environmental information improving the possibilities of ac...

Deep learning (DL) algorithms have already proved their effectiveness on a wide variety of application domains, including speech recognition, natural language processing, and image classification. To foster their pervasive adoption in applications where low latency, privacy issues and data bandwidth are paramount, the current trend is to perform in...

Cyber-Physical Systems (CPS) are embedded computational collaborating devices, capable of sensing and controlling physical elements and, often, responding to humans. Designing and managing systems able to respond to different, concurrent requirements during operation is not straightforward, and introduce the need of proper support at design-time an...

Technical Requirements (TRs) provide a "black box" conceptualization of the target project results with explicit verification tests. The goal of Technical Requirements Elicitation (TRE) is to ensure that all needs of involved stakeholders are being identified and adequately addressed without prescribing how to achieve them. Whilst TRE methodology i...

Cyber Physical Systems are highly adaptive systems, prone to change behaviour due to external/internal conditions. From the computation point of view, reconfigurable systems may address adaptation. In this paper, by a set of examples we show how coarse-grained reconfiguration may successfully allow achieving dynamic trade-off management, while cons...

This paper presents a new methodology for design and implementation of signal processing systems on system-on-chip (SoC) platforms. The methodology is centered on the use of lightweight application programming interfaces for applying principles of dataflow design at different layers of abstraction. The development processes integrated in our approa...

Domain-specific acceleration is now a “must” for all the computing spectrum, going from high performance computing to embedded systems. Unfortunately, system specialization is by nature a nightmare from the design productivity perspective. Nevertheless, in contexts where kernels to be accelerated are intrinsically streaming oriented, the combinatio...

Novel Deep Learning (DL) algorithms show ever-increasing accuracy and precision in multiple application domains. However, some steps further are needed towards the ubiquitous adoption of this kind of instrument. First, effort and skills required to develop new DL models, or to adapt existing ones to new use-cases, are hardly available for small- an...

Dataflow models of computation are capable of providing high-level descriptions for hardware and software components and systems, facilitating efficient processes for system-level design. The modularity and parallelism of dataflow representations make them suitable for key aspects of design exploration and optimization, such as efficient scheduling...

Applicable in different fields and markets, low energy High Efficiency Video Coding (HEVC) codecs and their constituting elements have been heavily studied. Fractional pixel interpolation is one of its most costly blocks. In this paper, a Field Programmable Gate Array (FPGA) implementation of HEVC fractional pixel interpolation, outperforming liter...

Modern embedded systems, to accommodate different applications or functionalities over the same substrate and provide flexibility at the hardware level, are often resource redundant and, consequently, power hungry. Therefore, dedicated design frameworks are required to implement efficient runtime reconfigurable platforms. Such frameworks, to challe...

In the last few years, besides the concepts of embedded and interconnected systems, also the notion of Cyber- Physical Systems (CPS) has emerged: embedded computational collaborating devices, capable of sensing and controlling physical elements and, often, responding to humans. The continuous interaction between physical and computing layers makes...

In the last years, the idea to dynamically interface biological neurons with artificial ones has become more and more urgent. The reason is essentially due to the design of innovative neuroprostheses where biological cell assemblies of the brain can be substituted by artificial ones. For closed-loop experiments with biological neuronal networks int...

Many embedded video-based systems require a video codec to reduce the bitrate prior to exchange video information. MPEG High Efficiency Video Coding (HEVC) is the latest, most efficient codec developed by the MPEG group. In the context of HEVC decoding, the optimization of the motion compensation stage is a daunting task. Recently, software impleme...

An important research problem, at the basis of the development of embedded systems for neuroprosthetic applications, is the development of algorithms and platforms able to extract the patient’s motion intention by decoding the information encoded in neural signals. At the state of the art, no portable and reliable integrated solutions implementing...

Dataflow modeling techniques facilitate many aspects of design exploration and optimization for signal processing systems, such as efficient scheduling, memory management, and task synchronization. The lightweight dataflow (LWDF) programming methodology provides an abstract programming model that supports dataflow-based design and implementation of...

Coarse-grained reconfigurable systems are capable of providing flexibility and optimal performance, suitable for nowadays embedded computing systems. The RPCT project has tackled the issue of their complex design, debug and mapping. Demonstration of its potentials and features are presented on an MPEG HEVC motion compensation use case.

Modern MPSoC architectures incorporate tens of processing elements on a single die. This trend poses the need of expressing the parallelism of the applications in order to effectively exploit the available resources. Several models of computation have been proposed, that specify an application as a network of independent computational elements. Suc...

In this paper, we propose a reconfigurable design of the Advanced Encryption Standard capable of adapting at runtime to the requirements of the target application. Reconfiguration is achieved by activating only a specific subset of all the instantiated processing elements. Further, we explore the effectiveness of power gating and clock gating metho...

Power reduction is one of the biggest challenges in modern systems and tends to become a severe issue dealing with complex scenarios. To provide high-performance and flexibility, designers often opt for coarse-grained reconfigurable (CGR) systems. Nevertheless, these systems require specific attention to the power problem, since large set of resour...

In this paper we target the design of a dedicated low-power computing platform for neuroprosthetic applications. The system must be capable of decoding the information encoded in neural signals, to extract the patients’ motion intention. To this aim, a highly-portable and reliable integrated processing device is required. However, a commonly acknow...

This paper focuses on how to efficiently reduce power consumption in coarse-grained reconfigurable designs, to allow their effective adoption in heterogeneous architectures supporting and accelerating complex and highly variable multifunctional applications. We propose a design flow for this kind of architectures that, besides their automatic custo...

The design of embedded systems for neuroprosthetic applications represents an important challenge to be faced in electronic bioengineering. One of the key research problems is decoding the information encoded in neural signals to extract the patient's motion intention. How to implement a highly-portable and reliable integrated solution is still an...

Advancements in CMOS technology enable the integration of a huge number of resources on the same system-on-chip. Managing the consequent growing complexity, including fault tolerance issues in deep submicron technologies, is a hard challenge for hardware designers. Self-organization may represent a viable path toward the development of massively pa...

The implementation of processing platforms supporting multiple applications by runtime reconfigurations on dedicated hardware modules requires the solution of different problems. These problems are notably not-trivial since both platform and application complexities increase year after year. As a consequence, the design process is both time and res...

Modern embedded systems designers are required to implement efficient multi-functional applications, over portable platforms under strong energy and resources constraints. Automatic tools may help them in challenging such a complex scenario: to develop complex reconfigurable systems while reducing time-to-market. At the same time, automated methodo...

Complexity management, portability and long term adaptivity are common challenges in different fields of embedded systems, normally colliding with the needs of efficient resource utilization and power balance. Image/signal processing systems, though required to offer a large variety of complex functions, have also to deal with battery-life limitati...

Power reduction in modern embedded systems design is a challenging issue exacerbated by the complexity and heterogeneity of their architecture. In the field of Reconfigurable Video Coding (RVC), to challenge these issues and cut-down time to market, dataflow-based techniques have been adopted. In particular, to master management and composability o...

Applications and hardware complexity management in modern systems tend to collide with efficient resource and power balance. Therefore, dedicated and power-aware design frameworks are necessary to implement efficient multi-functional runtime reconfigurable signal processing platforms. In this work, we adopt dataflow specifications as a starting poi...

Hardware accelerators are widely adopted to speed up computationally onerous applications. However their design is not trivial, especially if multiple applications/kernels need to be served. To this aim the Multi-Dataflow Composer (MDC) tool can be adopted to generate the internal computing core of flexible and reconfigurable hardware accelerators....

Specialized hardware infrastructures for efficient multi-application runtime reconfigurable platforms require to address several issues. The higher is the system complexity, the more error prone and time consuming is the entire design flow. Moreover, system configuration along with resource management and mapping are challenging, especially when ru...

Spike sorting is a critical task in neural signal decoding because of its computational complexity. From this perspective, the research trend in the last years aimed at designing massively parallel hardware accelerators. However, for implantable system with a reduced number of channels, as could be those interfaced to the Peripheral Nervous Systems...

The implementation of multi-context systems over coarse-grained reconfigurable platforms could bring several benefits in terms of efficient resource usage and power management. Nevertheless on-the-fly reconfiguration and mapping are not so straightforward and the optimal configuration of the substrate could be extremely time consuming. In this pape...

In the last few years, efficient resource management turned out to be one of the major challenges for hardware designers. Strategies of reusability through reconfiguration have demonstrated interesting potentials to address it, providing also power and area minimization. The Multi-Dataflow Composer (MDC) tool has been presented to the scientific co...

In the last few years, efficient resource management turned out to be one of the major challenges for hardware designers. Strategies of reusability through reconfiguration have demonstrated interesting potentials to address it, providing also power and area minimization. The Multi-Dataflow Composer (MDC) tool has been presented to the scientific co...

The manual creation of specialized hard-ware infrastructures for complex multi-purpose systems is error-prone and time-consuming. Moreover, lots of effort is required to define an optimized and heterogeneous components library. To tackle these issues, we propose a novel design flow based on the Dataflow Process Networks Model of Computation. In par...

Massively Parallel Systems-on-chip represent the new frontier of integrated computing systems for general purpose computing. The integration of a huge number of cores poses several issues such as the efficiency and flexibility of the interconnection network in order to serve in the best way the different traffic patterns that can arise. In this pap...

High-level synthesis (HLS) aims at reducing the time-to-market by providing an automated design process that interprets and compiles high-level abstraction programs into hardware. However, HLS tools still face limitations regarding the performance of the generated code, due to the difficulties of compiling input imperative languages into efficient...

Dataflow specifications are suitable to describe both signal processing applications and the relative specialized hardware architectures, fostering the hardware–software development gap closure. They can be exploited for the development of automatic tools aimed at the integration of multiple applications on the same coarse-grained computational sub...

On the wave of technology scaling, digital designers are quickly approaching the limits of current technologies. At the same time, deep submicron architectures are becoming more prone to transient errors and permanent faults. Swarm intelligence represents an interesting source of inspiration already used in the past for the design of decentralized-...

Dataflow Model of Computation (D-MoC) is particularly suitable to close the gap between hardware architects and software developers. Leveraging on the combination of the D-MoC with a coarse-grained reconfigurable approach to hardware design, we propose a tool, the Multi-Dataflow Composer (MDC) tool, able to improve time-to-market of modern complex...

This paper presents a novel Network on Chip able to offer flexibility to multi-threaded heterogeneous traffic applications typical of massive multicore chips. It combines different switching types and data control flow protocols, allowing to reprogram on the fly the total amount of bandwidth available per switching type. In principle this can be ea...

Multi-Processors System on Chip (MPSoCs) and Massively Parallel Processors (MPPs) architectures are conceived to efficiently implement Thread Level Parallelism, a common characteristic of modern software applications targeted by embedded systems. Each core in a MPP environment is designed to execute a particular instructions flow, known as thread,...

The Reconfigurable Video Coding (RVC) framework is a recent ISO standard aiming at providing a unified specification of MPEG video technology in the form of a library of components. The word “reconfigurable” evokes run-time instantiation of different decoders starting from an on-the-fly analysis of the input bitstream. In this paper we move a first...

The growing complexity of digital architectures strongly impacts on their verification phase, which becomes critical. In fact, without giving up cycle-accuracy, it seems there are not at the state-of-the-art fast frameworks allowing multi-parametric simulations at a fine granularity level for accurate verification and design space exploration purpo...