# Franc BrglezNorth Carolina State University | NCSU · Department of Computer Science

Franc Brglez

Ph. D.

Engaged in measuring asymptotic first-passage-time performance of combinatorial optimization solvers on hard problems

## About

149

Publications

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Introduction

## Publications

Publications (149)

We consider instances of bipartite graphs and a number of asymptotic performance experiments in three projects: (1) top movie lists, given databases of movies and viewers, (2) maximum matchings, and (3) minimum set covers. Experiments are designed to measure the asymptotic runtime performance of abstract data types (ADTs) in three programming langu...

A rigorous empirical comparison of two stochastic solvers is important when one of the solvers is a prototype of a new algorithm such as multiwalk (MWA). When searching for global minima in $\mathbb{R}^p$, the key data structures of MWA include: $p$ rulers with each ruler assigned $m$ marks and a set of $p$ neighborhood matrices of size up to $m(m-...

The search for binary sequences with a high figure of merit, known as the low autocorrelation binary sequence (labs) problem, represents a formidable computational challenge. To mitigate the computational constraints of the problem, we consider solvers that accept odd values of sequence length L and return solutions for skew-symmetric binary sequen...

Search for binary sequences with a high figure of merit, also known as the
low autocorrelation binary sequence problem, represents a formidable
computational challenge. In 2003, two stochastic solvers reported computational
complexity of $O(1.423^L)$ and $O(1.370^L)$, refined to $O(1.5097^L)$ and
$O(1.4072^L)$ for L odd in this paper. The solvers f...

Self-avoiding walks (SAWs) were introduced in chemistry to model the
real-life behavior of chain-like entities such as solvents and polymers, whose
physical volume prohibits multiple occupation of the same spatial point. In
mathematics, a SAW lives in the n-dimensional lattices.
In this paper, SAWs are a metaphor for walks across faces of n-dimensi...

When throwing a solid object like a hexahedron, an octahedron or a tetrakis-hexahedron on a flat surface, we expect it to roll onto any of the faces with probabilities of exactly 1/6, 1/8, or 1/24, respectively. Informally, we view such objects as instances from the n-dimensional dice family; formally, they are instances from a hyperhedron family ℋ...

After extensive experiments with two algorithms, CPLEX and our implementation of all-integer dual simplex, we observed extreme differences between the two on a set of design automation benchmarks. In many cases one of the two would find an optimal solution within seconds while the other timed out at one hour.
We conjecture that this contrast is acc...

Combinatorial optimization problems expressed as Boolean constraint satisfaction problems (BCSPs) arise in several contexts, ranging from the classical unate set-packing problems to the binate minimum cover problems, including the Haplotype Inference by Pure Parsimony (HIPP) problem. These problems are being solved under different formulations and...

After extensive experiments with two algorithms, CPLEX and our implementation of all-integer dual simplex, we ob- served extreme dierences between the two on a set of de- sign automation benchmarks. In many cases one of the two would find an optimal solution within seconds while the other timed out at one hour. We conjecture that this contrast is a...

Covering problems arise in many areas of electronic design automation such as logic minimization and technology mapping. An exact solution can critically impact both size and performance of the devices being designed. This paper introduces eclipse, a branch-and-bound solver that can solve many covering problems orders of magnitude faster than exist...

A recent series of experiments with a group of state-of-the-art SAT solvers and several well-defined classes of problem instances reports statistically significant performance variability for the solvers. A systematic analysis of the observed performance data, all openly archived on the Web, reveals distributions which we classify into three broad...

The low-autocorrelation binary sequence (LABS) problem represents a major chal-lenge to all search algorithms, with the evolutionary algorithms claiming the best results so far. However, the termination criteria for these types of stochastic algorithms are not well-defined and no reliable claims have been made about optimality. Our approach to find...

Advances in local-search SAT solvers have traditionally been presented in the context of local search solvers only. The most recent and rather comprehensive comparisons between UnitWalk and several versions of WalkSAT demonstrate that neither solver dominates on all benchmarks. QingTing2 (a 'dragonfly' in Mandarin) is a SAT solver script that relie...

This paper introduces a persistent agent called a skeptic who supplies instances from well-defined equivalence classes to test and benchmark SAT solvers. On such classes, metrics such as max/min ratio of time-to-solve should approach the value of 1.0. Experiments suggested by the skeptic on instances from the same class show (1) the time-to-solve m...

This paper introduces a persistent agent called skeptic who supplies instances from well-defined equivalence classes to test and benchmark SAT solvers. On such classes, metrics such as max/min ratio of time-to-solve should approach the value of 1.0. Experiments suggested by the skeptic on the instances of the same class show (1) the time-to-solve m...

We introduce a universal client (OmniFlow) whose GUI can be readily configured by the user to invoke any number of applications, concurrently or sequentially, anywhere on the network. The design and the implementation of the client is based on the principles of taskflow-oriented programming, whereby we merge concepts from structured programming, ha...

become larger. The best results for dot are obtained on random trees, trees motivated by VLSI circuits, meshes, and hypercubes. ---Minimum spanning trees on random points within narrow rectangles provide experimental subjects whose minimum number of crossings approach 0 in a controllable fashion Source code, scripts for generating data, running heu...

. Traditional approaches to the measurement of performance for CAD algorithms involve the use of sets of so-called “benchmark
circuits.” In this paper, we demonstrate that current procedures do not produce results which accurately characterize the
behavior of the algorithms under study. Indeed, we show that the apparent advances in algorithms which...

We introduce a universal client (OmniFlow) whose GUI can be readily configured by the user to invoke any number of applications, concurrently or sequentially, anywhere on the network. The design and the implementation of the client is based on the principles of taskflow-oriented programming, whereby we merge concepts from structured programming, ha...

Taskflow-oriented programming merges concepts from structured programming, hardware description, and mark-up languages. A mark-up language such as XML supports a well-defined schema that can capture the decomposition of a program into a hierarchy of tasks. A hardware description language such as VHDL relies on well-defined and explicit input/output...

The rapid advances in computing and networking technologies continue to stimulate formations of distributed teams worldwide. The advantages of an effective distributed design environment of tools, databases, and data management include the opportunity for a rapid assembly of a project-specific team of specialists who can immediately contribute towa...

A few years ago, during a well-attended open Design Automation Conference benchmark forum, a panellist pointed out that "...reporting experimental results is a science and an art. A survey of the literature may reveal a consistent methodology.... Also, we should address the verification of reported results." In retrospect, the suggestion may have h...

This paper is motivated by the need to generate classes of circuits that are closely related. Ideally, such circuits not only have identical size and distributions of cells and nets but also resemble each other closely in terms of cell clusters and interconnect patterns. Such classes are essential for welldefined performance evaluation of layout al...

OpenDesign is an open user-configurable project environment that
supports distributed collaborative design and execution on the Internet.
The environment is created by configuring a generic client for a
specific project. This is in contrast to an implementation of a
project-specific client-server architecture. This paper introduces the
OpenDesign e...

Traditionally, a single-user client application is rendered collaborative either by sharing its view or by re-writing it as a collaborative client. However, it may not be possible to anticipate in advance all preferences for collaboration, hence such a client may appear confusing to some users. We propose a novel client/server architecture for tk-b...

This paper presents a class software project that was part of a recent experimental graduate course on Frontiers of Collaborative Computing on the In- ternet. We chose Tcl/Tk to facilitate rapid proto- typing, testing, and demonstrating all phases of the project. The major milestones achieved during this course are: rapid proficiency in Tcl/Tk that...

Traditionally, a stand-alone client application is rendered collaborative for members of a team either by sharing its view or by re-writing it as a collaborative client. However, it may not be possible to anticipate in advance all preferences for collaboration, hence such a client may appear confusing to some of the team members.

A few years ago, during a well-attended open Design Automation Conference benchmark forum,1 a panelist pointed out that "...reporting experimental results is a science and an art. A survey of the literature may reveal a consistent methodology.... Also, we should address the verification of reported results." In retrospect, the suggestion may have h...

This paper presents a class software project that was part of a recent experimental graduate course on Frontiers of Collaborative Computing on the Internet. We chose Tcl/Tk to facilitate rapid prototyping, testing, and demonstrating all phases of the project. The major milestones achieved during this course are: • rapid proficiency in Tcl/Tk that a...

Experimental Design, as defined in science and manufacturing,
relies on data sets that belong to well-defined equivalence classes.
This paper introduces a method to generate tightly controlled
equivalence classes of circuit mutants, given the graph-based
characterization of a reference netlist, which an general may contain
cycles. A set of experime...

This paper introduces the background and motivation for the two
special sessions at ISCAS'99. The sessions bring together eight papers,
each rooted in the methodology of experimental design, and contributed
by collaborating teams of distributed participants. The paper briefly
outlines the premises of the companion papers that follow, provides a
bri...

Reduced, ordered binary decision diagrams (here, simply BDDs) have
been adopted as an important data structure for a number of
applications, ranging from logic design verification to logic
minimization and technology mapping. However, for a number of functions
that arise in practical applications, the size of the BDD data structure
depends critical...

The bigraph crossing problem, embedding the two node sets of a
bipartite graph G=(V<sub>0</sub>, V<sub>1</sub>, E) along two parallel
lines so that edge crossings are minimized, has application to placement
optimization for standard cells and other technologies. Iterative
improvement heuristics involve repeated application of some
transformation on...

The emerging web-based technologies can play an important role to instill the discipline of Experimental Design and make collaborative planning, executing, reporting, and archiving of experiments with core algorithms in CAD a routine. This paper introduces a user-configurable, cross-platform executable encapsulation environment that supports (1) un...

Reduced, Ordered Binary Decision Diagrams (here, simply BDDs) have been adopted as an important data structure for a number of applications, ranging from logic design verification to logic minimization and technology mapping. However, for a number of functions that arise in practical applications, the size of the BDD data structure depends critical...

The bigraph crossing problem, embedding the two vertex sets of a bipartite graph G = (V
0; V
1; E) along two parallel lines so that edge crossings are minimized, has application to circuit layout and graph drawing. We consider the case where both V
0 and V
1 can be permuted arbitrarily — both this and the case where the order of one vertex set is f...

Traditionally, the algorithms that optimize placement of cells in a VLSI layout rely on a cost function that includes a distance metric. The choice of a cost function may limit the choices in devising new, more efficient and more effective algorithms. The metric we propose relies on the interval graph of net nodes, induced by each specific placemen...

. This report introduces an experimental design that discovers a new relationship between a cell placement for minimized wire crossing in bipartite (two-layer) graphs and a cell placement in linear arrangement, optimized for minimum total wire length as measured after rectilinear routing in a single channel. We introduce hypercrossing, a new crossi...

. The increasing accessibility of heterogeneous `point tools' on the Web raises the question on how to best encapsulate such tools in order to create (1) simple-to-use workflows of task-specific tools and data, (2) communication channels between distributed participants to coordinate the collaborative control and execution of the workflow until all...

Applying the design of experiments methodology to the evaluation of BDD variable ordering algorithms has yielded a number of conclusive results. The methodology relies on the equivalence classes of functionally perturbed circuits that maintain logic invariance, or are within (1, 2, ...)-minterms of the original reference circuit function, also main...

This paper addresses issues that arise when a peer group, distributed across several time zones, uses the Internet to configure and execute distributed desktop-based applications and tasks. The paper provides solutions and Tcl/Tk implementations to support (1) peer-to-peer communication/control of distributed software and computing resources over t...

The WebWiseTclTk toolkit is an enhancement of the existing feature set of Safe-Tcl and Safe-Tk that does not compromise security. The toolkit re-defines the functionality of the auto load mechanism in Tcl such that it works for packages located anywhere on the World Wide Web. It also re-introduces several commands not available in Safe-Tk such as t...

. More than a thousand mathematical problems arising in engineering and science have been shown to be NP-hard. Problems of practical size that are NP-hard can only be solved by devising polynomial-time heuristics, with no guarantee whatsoever on the quality of the solution. Extensive experimentation and comparative analysis is required before we ca...

. Today, Web browsers provide a convenient access to the Internet while (1) increasing the number of useful desktop functions, and, (2) reducing the platform dependence on the operating system of the host. This paper introduces a toolkit WebWiseTclTk and demonstrates a range of its applications in support of a heterogeneous computing environment wh...

Despite more than a decade of experience with the use of standardized benchmark circuits, meaningful comparisons of EDA algorithms remain elusive. In this paper, we introduce an entirely new methodology for characterizing the performance of Binary Decision Diagram (BDD) software. Our method involves the synthesis of large equivalence classes of Ent...

This paper presents a Tcl/Tk recording/playback architecture and implementation that records, plays back and executes a Tcl/Tk collaborative Internet-based desktop. Specifically, the desktop brings together distributed data, application workflows, and teams into collaborative sessions in which the control of the desktop editing and execution is sha...

Today, web browsers provide a convenient access to the Internet while (1) increasing the number of useful desktop functions, and, (2) reducing the platform dependence on the operating system of the host. This paper introduces OmniDesk, implemented as an applet, that creates a userconfigurable desktop within the web browser window. User can place an...

This paper formalizes the synthesis process of wiring signature-invariant (WSI) combinational circuit mutants. The signature \sigma_0 is defined by a reference circuit \eta_0, which itself is modeled as a canonical form of a directed bipartite graph. A wiring perturbation \gamma induces a perturbed reference circuit \eta_{\gamma}. A number of mutan...

Despite more than a decade of experience with the use of standardized benchmark circuits, meaningful comparisons of EDA algorithms
remain elusive. In this paper, we introduce a new methodology for characterizing the performance of Binary Decision Diagram
(BDD) software. Our method involves the synthesis of large equivalence classes of functionally...

WAve Synthesis of Permissible mutation functions, WASP, is a heuristic with an objective to minimize the nodes and the levels of an acyclic multiple level boolean network of 2-input nodes. WASP transforms a multi-input, multi-output perturbation region of wires P j into a single-level mutation subcircuit M j and a remainder subcircuit R j . The tra...

This is the final report of the National Benchmark Program in Microelectronic Systems Design Automation. This project was initiated on the premise that by leveraging the evolving technologies of the Internet, one can greatly improve the ad hoc benchmarking efforts of the past decade. Specifically, using the Internet, we have laid the groundwork for...

We conjecture that good column-based placements can be produced by minimizing two wire crossing numbers: (1) the total wire crossing of all edges between cells in the wiring channel, and (2) the maximum wire crossing on the imaginary cutlines that separate cells on the opposite ends of the channels. We leverage the canonical form of the multi-level...

# This paper introduces a directed hypergraph model that supports #1# work#ow composition and recon#guration while accessing and executing programs, data, and computing resources across the Internet, #2# synchronous and asynchronous peer-to-peer interaction between members of any team during work#ow composition and execution, #3# synchronous and as...

The Internet-based desktop environment as defined in this paper consists of a cross-platform browser, a number of server icons (host nodes), a number of application icons (program nodes) and a number of data icons (file nodes). In contrast to typical desktops of today, where data icons may be dragged and dropped onto application icons for execution...

Tasks in a distributed benchmarking or design environment are complex and variable. A single paradigm is not suitable for all tasks and teams, and a paradigm that suits a task and a team for some time may not be suitable for all of the time. The notion of a collaborative workflow as introduced in this paper is founded on a reconfigurable and compos...

Current approaches to partial scan may not necessarily cover all faults, in particular the faults introduced by the partial scan chain (or the test machine) itself. Typically, the user does not have complete control on the fault coverage achieved by the partial scan. In this paper, we introduce a new partial scan assignment algorithm that not only...

We present a method for testing sequential circuits using weighted random sequences. The weights are stored and a weighted random sequence generator is used to produce the required test sequences during testing rather than storing the actual test sequences themselves. The generation of required weights is based on the dynamic scan algorithm, DYNAST...

Today, typical experiments that report `performance' of EDA algorithms are based on isolated instances of circuit benchmarks. In this paper, we design and report results of experiments that use a large number of sample circuits from several equivalence classes. We consider a number of known circuit benchmarks and construct large samples of circuits...

This report applies the synthesis of recently introduced equivalence class of circuit mutants within the context of benchmarking applications that range from logic synthesis and technology mapping to variable ordering of BDDs. Mutants in a given equivalence class are NOT random circuits. The signature-invariant property of the class induces synthes...

This paper introduces an environment for encapsulation and benchmarking of prototype algorithms in a context of realistic design flows. Application--specific parsers read the benchmark descriptions; standardized report generators summarize the benchmarking experiments. Tcl/Tk is used to implement the user interface, describe dynamically reconfigura...

This paper introduces a technique to transform a given RT-Level design, consisting of control logic and data path, into a functionally equivalent, minimized design which is 100% testable under full-scan at the gate level. The proposed RT-Level optimization technique uses the RT-Level structure and exploits the interaction between the control and th...

This paper analyzes the effect of resource sharing and assignment on the clock period of the synthesized circuit. The assignment phase assigns or binds operations of the scheduled behavioral description to a set of allocated resources. We focus on control-flow intensive descriptions, characterized by the presence of mutually exclusive paths due to...

This paper addresses the problem of true delay estimation during high level design. The existing delay estimation techniques either estimate the topological delay of the circuit which may be pessimistic, or use gate-level timing analysis for calculating the true delay, which may be prohibitively expensive. We show that the paths in the implementati...

This paper presents a new method,based onMarkov chain analysis, to evaluate the performance of schedules of behavioral specifications. The proposed performance measure is the expected number of clock cycles required by the schedule for a complete execution of the behavioral specification for any distribution of inputs. The measure considers both th...

This paper addresses the problem of true delay estimation during
high level design. The true delay is the delay of the longest
sensitizable path in the resulting circuit, as opposed to the
topological delay which is the delay of the longest path in the circuit.
The existing delay estimation techniques either estimate the topological
delay, which ma...

In this paper, we introduce a new recursive partitioning paradigm PROP which combines partitioning, replication, optimization, to be followed by another recursion of partitioning, etc. We measure the quality of partitions in terms of total device cost, logic and terminal utilization, and critical path delay. Traditionally, the minimum lower bound i...

With current approaches to partial scan, it is difficult, and often impossible, to achieve a specific level of fault coverage without returning to fill scan. In this paper, we introduce a new formulation of the minimum scan chain assignment problem and propose an effective covering algorithm and test sequence generator SCORCH (Scan Chain Ordering w...

This paper introduces the concept of detectable perturbations as a
method to generate tests that can then cover any technology-specific
faults such as multiple bridging, open and stuck-at faults. Rather than
devising a customized test pattern generation system for each class of
technology-specific faults, we implemented a generic system to generate...

This paper presents a new method, based on Markov chain analysis, to evaluate the performance of schedules of behavioral specifications. The proposed performance measure is the expected number of clock cycles required by the schedule for a complete execution of the behavioral specification for any distribution of inputs. The measure considers both...

This paper considers the problem of partitioning a large logic circuit into a collection of subcircuits each of which is implemented with a device from a specific (FPGA) library. The objective function that we minimize is not only the total cost of devices to be used in the partition but also the size of the interconnect between the devices. We int...

This paper analyzes the effect of resource sharing and assignment on the clock period of the synthesized circuit. We focus on behavioral specifications with mutually exclusive paths, due to the presence of nested conditional branches and loops. It is shown that even when the set of available resources is fixed, different assignments may lead to cir...

Under sponsorship of the National Science Foundation, eleven participants from universities and industry and seven individuals from the NSF met during October 18-19, 1993, to assess the unique needs educators have for rapid prototyping of microelectronic systems and to suggest potential solutions for continuously improving the state-of-the-art in U...

This paper introduces the concept of functional replication and a unified cost model for min-cut partitioning with replication. We apply this concept to the problem of partitioning lar e logic circuits into a collection of subcir- cuits each of w 8. Ich is implemented with a device from a specific (FPGA) librar We measure the quality of each k-way...

This paper introduces the concept of a permissible bridge and a
permissible bridge pair. A bridge is a logic node with two inputs and
one output. A bridge or a bridge pair are called permissible if they can
be inserted into a Boolean network without changing its behavior at
primary outputs. There are a total of 255 types of bridges that can be
cons...

This paper introduces a functionality fault model and demonstrates
its feasibility and advantages. In current designs, the fanin of logic
modules implemented in CMOS standard cell, mask-programmable, or
field-programmable gate array technology, rarely exceeds 4 on the
average. A functionality fault model, based on complete enumeration of
the truth...

This paper considers the problem of obtaining a minimum-cost partitioning of a large logic circuit into a collection of subcircuits implementable with devices selected from a given library. Each device in the library may have a different price, size, and terminal capacity. We propose a multi-way partitioning algorithm based on a recursive applicati...

A new method for quickly retrieving Boolean functions from an
arbitrarily large library is introduced. The method relies on signature
calculation for variables of Boolean functions. Signatures induce an
ordering of the variables which is used to construct a BDD (binary
decision diagram). The potential of the method is demonstrated by an
application...

The weights are stored and a weighted random sequence generator is
used to produce the required test sequences during testing rather than
storing the actual test sequence themselves. The generation of required
weights is based on the dynamic scan algorithm, DYNASTEE. Experimental
results demonstrate tradeoffs in test application time and in tester...

The authors introduce a technique to transform a given RT-level
design into a functionality equivalent, minimized design which is 100%
testable under full-scan at the gate level. The proposed optimization
technique uses the RT-level structure and exploits the interaction
between the control and the data path. The approach maintains the design
hiera...

A behavioral model of a class of mixed hardware-software systems is presented. A codesign methodology for such systems is defined. The methodology includes hardware-software partitioning, behavioral synthesis, software compilation, and demonstration ...

The authors re-examine the concept of test machine embedding and present a new test machine architecture: cellular scan. Unlike the traditional scan machine architecture, the cellular scan machine requires no scan-out pin. A dynamic scan test generation algorithm, DYNASTEE, is introduced. It reduces test sequence length when compared to existing st...

The authors introduce characteristic signatures for Boolean functions. The signatures do not exhibit sensitivity to permutations of input variables. These signatures are used to develop a method of rapidly matching subcircuits with cells in a large library. The procedure is analogous to hashing. Filters are discussed that were found to be useful in...