Fernando Adolfo Escobar Juzga

Imagination Technologies

High Performance Computing (HPC) systems currently integrate several resources such as multi-cores (CPUs), graphic processing units (GPUs) and reconfigurable logic devices, like Field Programmable Gate Arrays (FPGAs). The role of the latter two has traditionally being confined to act as secondary accelerators rather than as main execution units. We...

Branch-and-Bound (B&B) algorithms are one of the most employed techniques in optimization problems. Its complexity increases exponentially with problem size and features a challenging dynamic memory management caused by recursive processing. Most solutions focus on parallel branch evaluation in multi-core CPUs or GPUs. To the best of our knowledge,...

FPGA-based platforms allow implementing reconfigurable systems that can change functionality of portions of hardware at runtime. For this purpose, non-volatile, off-chip storage is required to hold the partial-configuration bitstreams that will be used for reconfiguration. Accessing such devices requires a high CPU usage or a dedicated hardware suc...

Dynamic Programming (DP) is used to solve combinatorial optimization problems and constitutes one of the 13 High Performance Computing (HPC) patterns. DP suffers from irregular, data-dependent memory accesses that deteriorates performance. The Knapsack 0/1 belongs to the simplest DP algorithms which is called Serial Monadic and has been treated in...

Dynamic partial reconfiguration (DPR) is a technique that optimizes resource utilization of SRAM-based FPGAs, since it allows changing, on the fly, the functionality of a portion of its logic. A common DPR development flow requires the use of, at least, a microprocessor and several development tools (EDK, XSDK, PlanAhead); moreover, proposals are m...

Sound source localization in real time can be employed in numerous applications such as filtering, beamforming, security system integration, etc. Algorithms employed in this field require not only fast processing speed but also enough accuracy to properly cope with the application requirements. This work presents accuracy benchmarks of a hybrid app...

Networks on Chip (NoCs) are commonly used to integrate complex embedded systems and multiprocessor platforms due to their scalability and versatility. Modeling tools used at the functional level use SystemC to perform hardware–software co-design and error correction concurrently, thus, reducing time to market. This work analyzes a JPEG encoding al...

Sound source localization algorithms are usually complex at the computational level, to the point that only dedicated hardware architectures can meet the required realtime processing power. This paper analyses a previously proposed, single-source, location algorithm, which adapts in realtime its search spectrum, thus reducing its workload. The pro...

Network on Chip (NoC) is a new paradigm to intercommunicate modules on the same dice that propose the replacement of traditional buses by routers and interface cards. The router is the main agent affecting performance and functionality of the overall system as it is in charge of delivering the information efficiently and reliably. A validation of t...