Félix B. Tobajas

Félix B. Tobajas
Universidad de Las Palmas de Gran Canaria | ULPGC · Instituto Universitario de Microelectrónica Aplicada (IUMA)

PhD

About

81
Publications
25,110
Reads
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260
Citations
Introduction
Félix Tobajas was born in Zaragoza, Spain, in 1971. He received the M.S. and Ph.D. Degrees in Telecommunication Engineering from University of Las Palmas de Gran Canaria (ULPGC), Spain, in 1996 and 2001, respectively. He joined the Institute for Applied Microelectronics (IUMA) in 1993. In 2003 he received the best Ph.D. award from the Spanish Association of Telecommunication Eng. He has been awarded with two six years research periods by the National Agency for the Research Activity Evaluation.
Additional affiliations
June 1997 - present
Universidad de Las Palmas de Gran Canaria
Position
  • Professor (Associate)

Publications

Publications (81)
Article
Super-resolution (SR) covers a set of techniques whose objective is to improve the spatial resolution of a video sequence or a single frame. In this scope, fusion SR techniques obtain high-resolution (HR) frames taking as a reference several low-resolution (LR) frames contained in a video sequence. This paper is based on a selective filter to decid...
Article
Image spatial resolution is critical in several fields such as medicine, communications or satellite, and underwater applications. While a large variety of techniques for image restoration and enhancement has been proposed in the literature, this paper focuses on a novel Super-Resolution fusion algorithm based on a Multi-Camera environment that per...
Article
In recent years, Wireless Sensor Networks have experienced significant growth, mainly motivated by the development of standard communication protocols and the availability of low cost microcontrollers and wireless transceivers, resulting in low-power small-size sensing and data processing capable devices, and wireless communication links. In this p...
Article
Super-Resolution (SR) consists in processing an image or a set of images in order to enhance the resolution of a video sequence or a single frame. In this paper, fusion SR techniques are considered, where High-Resolution (HR) images are constructed from several observed Low-Resolution (LR) images, thereby increasing the high-frequency components an...
Conference Paper
Variable Size Block-Matching Super-Resolution covers a set of techniques which objective is to improve the resolution of a video sequence or a single frame considering variable sized Macro-Blocks. In this paper, this approach is combined with a Multi-Camera system to take advantage from the spatial and temporal correlations between frames.
Conference Paper
In this work, the factors of reduction of memory requirements and increase in memory traffic associated with the change from reference frame level (baseline algorithm) to macroblock-level for the Super-Resolution (SR) image restoration non-uniform grid projection algorithm are compared over combinations of algorithm parameter values. Then, based on...
Article
Super-Resolution (SR) covers a set of techniques whose objective is to improve the resolution of a video sequence or a single frame. In this scope, a fusion SR algorithm has been used, where High-Resolution (HR) images are constructed from several observed Low-Resolution (LR) images. In this paper, this approach is combined with a Multi-Camera (MC)...
Conference Paper
Full-text available
In this paper, the design of a Battery Management System for a battery pack composed of Lithium-Ion cells is described. It specifies which lithium-ion technology is used for monitoring control signals such as the high voltage per cell, the start voltage balancing, the low voltage shutdown, and the maximum temperature of battery cells pack. The prop...
Conference Paper
Georeferencing consists in establishing a relationship between information and geographic locations, usually through geospatial referencing (i.e., longitude and latitude coordinates). Super-Resolution is a technique that enhances the spatial resolution of an imaging system. In this paper, the integration of both Georeferencing and Super-Resolution...
Conference Paper
This contribution focuses on the experience gained in the adaptation of a peer mentoring program to effectively provide support for students with special needs, and in particular for engineering students with Asperger's Syndrome (AS) at university. A detailed description of the program after two years of existence is provided, including the specifi...
Conference Paper
Super-Resolution (SR) covers a set of techniques which objective is to improve the resolution of a video sequence or a single frame. In this scope, a fusion SR algorithm has been used, where High-Resolution (HR) images are constructed from several observed Low-Resolution (LR) images. In this paper, this approach is combined with a Multi-Camera (MC)...
Conference Paper
MultiProcessor Systems-on-Chip (MPSoC) are required to fulfill the performance demand of modern real-life embedded applications. For that purpose, Networks-on-Chip (NoC) are proposed as a promising solution to interconnection in MPSoCs for reasons of efficiency and scalability. In this scenario, the need to develop low-cost platforms to support NoC...
Conference Paper
Education focused on the student's learning is the new paradigm of learning process proposed by the European Higher Education Area (EHEA) to promote an improvement in quality and international competitiveness of higher education in Europe. The adoption of this student-centered paradigm of learning requires changes in teaching methods and tools whic...
Conference Paper
Super-Resolution (SR) is a set of techniques which objective is to increase and improve the resolution of an image or a video sequence. In this scope, one of the most used techniques is “fusion”, where High-Resolution (HR) images are constructed from several observed Low-Resolution (LR) images. In this paper, a fusion SR algorithm is enhanced intro...
Conference Paper
Current tendencies of consumer electronics have envisaged multiprocessor System-on-Chip (SoC) as a promising solution for the high performance embedding systems, and, in this scenario, Network-on-chip communication paradigm is considered as a way to improve on-chip communication efficiency. In this paper, a NoC based SoC emulation framework is desi...
Conference Paper
In recent years, IEEE 802.15.4-based Wireless Sensor Networks (WSN) have experienced significant growth, mainly motivated by the standard features, such as small size oriented devices, low power consumption nodes, wireless communication links, and sensing and data processing capabilities. In this paper, the development, implementation and deploymen...
Conference Paper
The necessity to improve image resolution is of great concern in multiple diverse fields such as: medicine, communications, or satellite and underwater applications. A high variety of techniques for image enhancement has been proposed in the literature, being a trade-off the relation between the computation time and the quality of the obtained resu...
Conference Paper
Multiprocessor systems-on-chip (MPSoC) are required to fulfill the performance demand of modern real-life embedded applications. These MPSoCs are employing Networkon-Chip (NoC) for reasons of efficiency and scalability. In this scenario, the need to develop low-cost platforms to support NoC design and verification is growing. Furthermore, in order...
Conference Paper
The necessity to improve image resolution is of great concern in multiple diverse fields such as: medicine, communications, or satellite and underwater applications. A high variety of techniques for image enhancement has been proposed in the literature, being a trade-off the relation between the computation time and the quality of the obtained resu...
Conference Paper
In recent years, Wireless Sensor Networks (WSN) have experienced significant growth, mainly motivated by low cost wireless transceivers and microcontroller availability, and by communication standard development, resulting in small size oriented, low power consuming, wireless communication links, and sensing and data processing capable devices. In...
Conference Paper
In recent years, Wireless Sensor Networks (WSN) have experienced significant growth, mainly motivated by low cost wireless transceivers and microcontroller availability, and by communication standard development, resulting in small size oriented, low power consuming, wireless communication links, and sensing and data processing capable devices. In...
Conference Paper
The necessity to improve image resolution is of great concern in multiple diverse fields such as: medicine, communications, or satellite and underwater applications. A high variety of techniques for image enhancement has been proposed in the literature; nevertheless it is necessary to fairly validate this improvement effectively. This work is focus...
Conference Paper
Full-text available
Though Peer Mentoring is often cited as among the most influential factors on retention rates and degree completion, that influence is difficult to assess. From the academic year 2007- 2008, the evaluation of the Mentoring Program of the Escuela Técnica Superior de Ingenieros de Telecomunicación (PM-ETSIT) at the University of Las Palmas de Gran Ca...
Article
Multiprocessor System-on-Chip (MPSoCs) are emerging as one of the technologies providing a way to support the growing design complexity of embedded systems including several types of cores. The interconnection among cores of a MPSoC is proposed to be provided by Networks-on-Chip (NoC). In real applications it is usual to find different interconnect...
Article
The growth of complexity and the requirements of on-chip technologies create the need for new architectures which generate solutions representing a compromise between complexity and power consumption, and Quality of Service (QoS) of the communications between the cores of a System-on-Chip (SoC). Network-on-Chip (NoC) arises as a solution to impleme...
Conference Paper
Nowadays, images are employed in several areas, as could be medicine, communications, cartography or in the military field. Various techniques for image enhancement have been proposed in the literature, but it is necessary to fairly validate this enhancement. This work is focused on a test environment that permits to compare, both qualitative and q...
Conference Paper
Nowadays, images are employed in several areas of medicine for early diagnosis. In this sense, the industry provides accurate models to obtain, for example, X-ray and cardiology images of high resolution. However, other images, such as those related to pathological anatomy present in many situations poor quality, which complicates the diagnostic pr...
Conference Paper
Full-text available
The Mentoring Program of the Escuela Técnica Superior de Ingenieros de Telecomunicación (ETSIT) is intended to establish a mechanism based on peer mentoring provided by upper-class students (Mentors) to provide help, support, and resources to incoming first-year students (Mentees). This paper focuses on the experience gained in the creation and dev...
Article
The possibility of increasing the spatial resolution of video sequences is becoming extremely important in present-day multimedia systems. In this sense, super-resolution represents a smart way to obtain high-resolution video sequences from a finite set of low-resolution video frames. This set of low-resolution images must be obtained under differe...
Article
Full-text available
In a short period of time, the multimedia sector has quickly progressed trying to overcome the exigencies of the customers in terms of transfer speeds, storage memory, image quality, and functionalities. In order to cope with this stringent situation, different hardware devices have been developed as possible choices. Despite of the fact that not e...
Article
Full-text available
In this paper a topological analysis of different IP distributions focusing on optimal memory placements in regular 2DMeshes has been performed. As case study, a real MPEG-4 decoder implementation with three memories was chosen. In order to study the influence of memories in the topology of the network, Arteris NoCexplorer tool was used. The result...
Article
Full-text available
In this paper, the hardware implementation of a scheduler with QoS support is presented. The starting point is a Differentiated Service (DiffServ) network model. Each switch of this network classifies the packets in flows which are assigned to traffic classes depending of its requirements with an independent queue being available for each traffic c...
Article
Full-text available
Most reconfigurable systems rely on FPGA technology. Among these ones, those which permit dynamic and partial reconfiguration, offer added benefits in flexibility, in-field device upgrade, improved design and manufacturing time, and even, in some cases, power consumption reductions. However, dynamic reconfiguration is a complex task, and the real b...
Article
This letter presents a novel approach for organizing computational resources into groups within H.264/AVC motion estimation architectures, leading to reductions of up to 75% in the equivalent gate count with respect to state-of-the-art designs.
Article
Motion estimation architectures play a fundamental role in nowadays real time video encoding systems. However, in spite of their relevance, the influence of the allocation of the computing resources in terms of the final area, power dissipation and processing speed of such architectures has not been studied in depth in the recent literature. In thi...
Conference Paper
Full-text available
In this paper, a real output queuing switch prototype implementation is presented. This implementation is based on a novel high speed multidrop backplane and a general purpose line card which includes a Virtex-II 6000 FPGA. This switch is named GMDS (Gigabit MultiDrop Switch) and its main features are the switch matrix replacement by the multidrop...
Article
In this paper, a novel hardware architecture for real-time implementation of the adaptive deblocking filtering process specified by the H.264/AVC video coding standard, is presented. The deblocking filter is a computationally and data intensive tool resulting in an increased execution time of both the encoding and decoding processes. The proposed a...
Conference Paper
In this paper, a novel hardware architecture for real-time implementation of the adaptive deblocking filtering process specified by the H.264/AVC standard, is presented. The proposed architecture is based on a double-filter strategy that results in a significant saving in filtering cycles, memory requirements and gate count when compared with state...
Conference Paper
A new approach for exploring different allocation alternatives of the computational resources within H.264/AVC motion estimation architectures is presented in this paper. The use of this methodology has motivated the introduction of a novel architecture able to process CIF@60fps sequences with a reduced equivalent gate count and dynamic power savin...
Conference Paper
In this paper a topological analysis of different IP distributions focusing on optimal memory placements in regular 2D-Meshes has been performed. As case study, a real MPEG-4 decoder implementation with three memories was chosen. In order to study the influence of memories in the topology of the network, Arteris NoCexplorer tool was used. The resul...
Conference Paper
Super-resolution is a smart process capable of generating images with a higher resolution than the resolution of the sensor used to acquire the images. Due to this reason, it has acquired a significant relevance within the medical community during the last years, especially for those specialties closely related with the medical imaging field. Howev...
Article
This letter presents an architecture based on a new double-filter strategy to perform the adaptive in-loop filtering process specified by the H.264/AVC standard. The proposed architecture shows considerable advantages, both in terms of hardware cost and latency, when compared with the approaches found in the most recent literature.
Article
Managing the complexity of designing Systems-on-Chip (SoC) containing billions of transistors requires decoupling computation from communication. Networks-on-Chip (NoC) have been proposed as a solution for managing this problem as they meet the reusability, scalability and parallelism requirements of these systems, while coping with power constrain...
Article
A novel variable length packet scheduling algorithm focused on real output queue reference architecture is presented in this paper. The main features of this packet scheduler development are the Quality of Service (QoS) and variable length packet support. The packet scheduler supports up to eight traffic classes which can be assigned up to two diff...
Article
In this paper, the implementation of a 900 MHz multiphase oscillator with sinusoidal outputs in SiGe technology is presented. The circuit is based on a differential cross-coupled topology formed by four differential LC-oscillators that provide eight output signals with 45deg phase differences. The whole circuit was implemented full-custom. The fina...
Conference Paper
In this paper, the implementation of a 2.5 Gbps 1:32 deserializer in SiGe BiCMOS technology using standard cells and ECL bipolar circuits in order to minimize power consumption, is presented. The deserializer is composed of two main circuits: a demultiplexer and a clock distribution network. The architecture of the demultiplexer is based on a tree...
Article
H.264/AVC is the most recent and promising international video coding standard developed by the ITU-T Video Coding Experts Group in conjunction with the ISO/IEC Moving Picture Experts Group. This standard has been designed in order to provide improved coding efficiency and network adaptation. In this sense, H.264/AVC provides superior features when...
Conference Paper
Maximum data rate in today's available multidrop backplanes is limited to 400 Mbps due to signal integrity concerns. In this paper, an experimental gigabit multidrop serial backplane for high-speed digital systems based on a novel asymmetrical broadband power splitter configuration with matching trace impedance, is presented. Experimental results o...
Conference Paper
A low cost VLSI architecture to compute the motion vectors required by the H.264/AVC video coding standard is presented in this paper. The possibility of avoiding motion estimation modes together with a novel partial distortion elimination strategy have been successfully incorporated in the proposed architecture, providing important savings in the...
Article
A multidrop backplane based on point-to-multipoint serial links enables interconnection between line cards without requiring a central switch fabric. However, maximum data rate in today's available multidrop serial links is limited to 400Mbps due to signal integrity concerns. In this paper, a novel gigabit multidrop serial link configuration for hi...
Article
Full-text available
The maximum data rate in today's available multidrop backplanes is significantly limited due to signal integrity concerns. In this brief, a novel gigabit multidrop serial link configuration for high-speed digital systems based on newly developed asymmetrical broadband power splitters with matching trace impedance, is presented. The proposed power s...
Conference Paper
Classification of Internet protocol (IP) packets has become a bottleneck for the effective operation of QoS capable routers. In this paper, a novel packet classification scheme for high performance routers on different QoS architectures, named split-engine packet classification (SPC), is proposed. The key feature of the presented architecture is it...
Article
Nowadays clock recovery units are key elements in high speed digital communication systems. For an efficient operation, this units should generate a low jitter clock based on the NRZ received data, and be tolerant to long absence of transitions. Architectures based on Hogge phase detectors have been widely used, nevertheless, they are very sensitiv...
Article
Nowadays digital networks require architectures based on standards that are implemented independently of the technology. Besides, these network specifications can easily change to include novel services. For these reasons, dominant trends are to design and verify systems at high level, prior to technology mapping. In this paper, a methodology is pr...
Article
Scheduling algorithms developed for virtual-output-queuing (VOQ) switches have focused on the throughput enhancement, rather than provide QoS guarantees for different priority levels. Presented, is a new scheduling scheme to effectively support real-time and data applications in VOQ switches with negligible complexity increment.
Conference Paper
Virtual output queue (VOQ) is an efficient architecture for high-speed switches because it combines the low cost of input-queuing with high performance of output-queuing. The achievable throughput and delay performance heavily depends on the scheduling algorithm used to resolve the contention for the same output ports in each cell slot. Most VOQ sc...
Conference Paper
In this paper, architectural, circuital and technological solutions for the implementation of key elements in real-time video processing systems are presented. Spatial transforms and motion estimation are identified as the most critical elements in terms of computational cost, power dissipation and area overhead. In order to support real time appli...
Article
This article describes an ATM transceiver implementation with add/drop function over Synchronous Digital Hierarchy (SDH) able to handle STM-16c (OC-48c) signals. The design has been developed using Vitesse HGaAs-IV technology using Direct Coupled FET Logic (DCFL) standard cells and obtaining, in this way, a logic gate level description which could...
Article
Today's data communication systems are demanding increasing off-chip data rates. To satisfy this demand, high-speed serial links are used, saving area and power dissipation compared to highly parallel buses. However, power dissipation and noise generated by this system is still a critical issue. In this article, a novel approach using differential...
Article
Mathematical morphology (MM) appears as a theory that can solve some drawbacks of the classical lineal image processing. Linear filters generate a spatial distortion from initial image, what gives as result that specific algorithms are usually needed for each process with a complexity that cannot be implemented in VLSI systems for real time image p...
Article
In this paper, the implementation and results obtained for a Gallium Arsenide (GaAs) multiplierless filter bank with applications on Two Dimensional Discrete Wavelet Transform (2D-DWT) are presented. Among the benefits offered by this architecture, its configurable characteristics, which allow affording input images with different sizes, as well as...
Article
Today's increasing data rates in digital communication circuits are demanding higher speeds in the interchip communication. This throughput can be achieved using high rate serial links. Good noise inmunity can be obtained by means of differential strategies and an important power reduction can be obtained by using current mode operation. In this pa...
Article
Mathematical Morphology appears as a theory that can solve some drawbacks of the classical lineal image processing. Linear filters generate a spatial distortion from initial image, what gives as a result that specific algorithms are usually needed for each process with a complexity that can not be implemented in VLSI systems for Real Time Image Pro...
Article
In this paper, the implementation and results obtained for a Gallium Arsenide (GaAs) multiplierless filter bank with applications on Two Dimensional Discrete Wavelet Transform (2D-DWT) are presented. Among the benefits offered by this architecture, its configurable characteristics, which allow affording input images with different sizes, as well as...
Article
Based on the recently introduced GaAs pseudo-dynamic latched logic, the authors present a new type of carry lookahead adder (CLA) which combines the benefits of 0.6 μm E/D MESFET technology with the above mentioned class of logic. Consideration is given to power dissipation, taking into account that for high levels of integration, techniques to red...
Article
In this paper, the architecture and the implementation of a complex fast Fourier transform (CFFT) processor using 0.6 /spl mu/m gallium arsenide (GaAs) technology are presented. This processor computes a 1024-point FFT of 16 bit complex data in less than 8 /spl mu/s, working at a frequency beyond 700 MHz, with a power consumption of 12.5 W. The arc...