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Publications (120)
Neuromorphic computing has recently emerged as a potential alternative to the conventional von Neumann computer paradigm, which is inherently limited due to its architectural bottleneck. Thus, new artificial components and architectures for brain-inspired computing hardware implementation are required. Bipolar analog memristive devices, whose resis...
Valence change memories, in which internal redox reactions control the change in resistance are promising candidates for resistive random access memories (ReRAMs) and neuromorphic computing elements. In this context, La2NiO4+δ (L2NO4), a mixed ionic‐electronic conducting oxide, well known for its highly mobile oxygen interstitial ions, emerges as a...
The ORCID identification number(s) for the author(s) of this article can be found under https://doi.org/10.1002/admt.202200329.
Metal oxide-based resistive random access memory devices are highly attractive candidates for next-generation nonvolatile memories, but the resistive switching phenomena remain poorly understood. This article focuses on the microscopic understanding of the initial forming step, which is decisive for the switching process. The integrated resistive s...
In this work, we propose a novel integration in order to significantly reduce the High Resistance State variability and to improve thermal stability in Oxide-based Resis-tive Random Access Memory (OxRRAM) devices. A novel device featuring a metallic liner, acting as a parallel resistance, is presented. To assess the effect of this solution, we comp...
For neuromorphic computing that mimics the human brain, digital memory has to turn analogue. A key scientific question is how to teach materials to adopt synaptic plasticity. In article 2000439, Stefan Petzold, Eszter Piros, and co‐workers use the novel technique of oxygen engineering on yttrium oxide and show that this particular material is a pro...
In this work, we propose a novel integration in order to significantly reduce the High Resistance State vari-ability and to improve thermal stability in Oxide-based Resistive Random Access Memory (OxRRAM) devices. A novel device featuring a metallic liner, acting as a parallel resistance, is presented. To assess the effect of this solution, we comp...
Resistance switching is studied in conductive bridge memory structures made from atomic layer deposited HfO2 and Ag active electrode. Inert electrode is varied by using different substrates (TiN, W, Pt). HfO2 crystallinity is modified by varying the deposition temperature (300/350 °C) and the film thickness (10/20 nm). Current–voltage characteristi...
In this work, we study the impact of roughness of TiN bottom electrode on the forming voltage of 1R TiN/HfO2/Ti/TiN based ReRAM devices. A novel and atypical strategy is proposed to induce a controlled roughness of the bottom electrode, using various plasma chemistries. The forming voltage is observed to be directly linked to the roughness of the b...
In this work, we study the impact of roughness of TiN bottom electrode on the forming voltage of 1R TiN/HfO2/Ti/TiN based ReRAM devices. A novel and atypical strategy is proposed to induce a controlled roughness of the bottom electrode, using various plasma chemistries. The forming voltage is observed to be directly linked to the roughness of the b...
Hafnia-based resistive memories technology has come to maturation and acceded to the market of nonvolatile memories. Nevertheless, the physical mechanisms involved in resistive switching are not yet fully understood and the numerous ab initio simulations studies have few many atomic-scale experimental counterparts. In this study we investigate the...
Forming and breaking a nanometer-sized conductive area are commonly accepted as the physical phenomenon involved in the switching mechanism of oxide resistive random access memories (OxRRAM). This study investigates a state-of-the-art OxRRAM device by in-situ transmission electron microscopy (TEM). Combining high spatial resolution obtained with a...
Although the implementation of multiple countermeasures, both hardware and software, are making integrated circuits more and more secure, the backside of a chip is still considered as a vulnerability regarding physical attacks.
A novel protection structure will be presented here, which consists in combining several elements to make it impossible fo...
In this article, the reliability of HfO2-based RRAM devices integrated in an advanced 28 nm CMOS 16 kbit demonstrator is presented. In order to improve the memory performance, a thin Al2O3 layer is inserted in the HfO2-based memory stack (TiN/Ti/HfO2/Al2O3/TiN). Thanks to extensive electrical characterizations on both single layer HfO2 and bilayer...
Resistance switching is studied in HfO2 as a function of the anode metal (Au,Cu, and Ag) in view of its application to resistive memories (resistive random access memories, RRAM). Current-voltage (I-V) and current-time (I-t) characteristics are presented. For Auanodes,resistance transition is controlled by oxygen vacancies (oxygen-based resistive r...
A process for obtaining an array of nanodots (212) for microelectronic devices, characterized in that it comprises the following steps:
deposition of a silicon layer (210) on a substrate (100, 132),
formation, above the silicon layer (210), of a layer (240) of a material capable of self-organizing, in which at least one polymer substantially forms...
In this work, we use ab initio simulations to explore neutral and charged Frenkel pair (FP) formation inside HfO2. FP plays a crucial role in the conductive filament (CF) formation. We explore two possible mechanisms for the FP formation, namely electron injection and electron detrapping. The existence of one of the two mechanisms or both depends o...
A back-end integrated Resistive Random Access Memory (ReRAM) (TiN/HfO2/Ti/TiN) in advanced 28nm CMOS process is evaluated. Significant operating margins and high performances identified at device level (read margin, low power set/reset, endurance and retention) are demonstrated to be significantly reduced on larger statistics, i.e. characterized wi...
In this paper the effect of SET temperature on data-retention performances in HfO2-based RRAM has been thoroughly investigated. We demonstrated, for the first time to our knowledge, that high temperature programming (even if it has no influence on the initial resistance) has a strong effect on thermal stability of the conductive filaments. Moreover...
This paper proposes a novel pre-coding method that enables bypassing the soldering reflow issue in resistive memory devices called RRAM. This method is based on the difference between forming and set voltages distributions to discriminate virgin memory cells from those in which data were pre-coded before the soldering step. This procedure enables d...
This paper provides an overview of the temperature impact on the electrical behavior of oxide-based RRAM, during forming, low-field resistance reading, SET/RESET, disturb, data retention and endurance. HfO2-RRAM devices (in a 1T1R configuration) integrated in an advanced 65 nm technology are studied for this aim. We show that forming operation is s...
A process for manufacturing a stacked structure comprising at least one thin layer bonded to a target substrate, in which a thin layer is formed by introduction gaseous species into an initial substrate, to form a weakened layer separating a film from the rest of the initial substrate, a first contact face of the thin layer is bonded to a face of a...
Emerging nonvolatile memories based on resistive switching mechanisms pull intense research and development efforts from both academia and industry. Oxide-based resistive random access memories (OxRAM) gather noteworthy performances, such as fast WRITE/READ speed, low power, high endurance, and large integration density that outperform conventional...
In this paper, the failure acceleration behavior of HfO2 based ReRAM under constant voltage and high temperature stresses is studied. We extract the activation energy from disturb measurements in the High Resistance State (HRS) for different dielectrics. Various Reset conditions are studied and correlated to the failure mechanism. Low activation en...
We show experimentally that the first reset operation of forming-free HfOx based RRAM devices is of bulk type where the reset current is area dependent. Moreover, the device pristine resistance shows a weak inverse proportionality to temperature, which we associate to a sub-stoichiometric HfOx matrix created during device fabrication. Finally, we u...
Among the emerging nonvolatile memories, the oxide-based Resistive Random Access Memories (OxRAM) are nowadays considered among the most promising solutions for replacing or complementing current non-volatile memories, based on Flash, in next memory generations. [1]. These memories belong to a family of two terminal devices that can be switched to...
This paper provides an overview of the temperature impact (up to 200 °C) on the electrical behavior of oxide-based RRAM, during forming, low-field resistance reading, SET/RESET, disturb, data retention and endurance. HfO2-RRAM devices (in a 1T1R configuration) integrated in an advanced 65 nm technology are studied for this aim. We show that forming...
This paper gives an overview of our research work on Oxide Resistive switching memory (OxRAM) at technology and design level. The OxRAM technology has been developed in order to be co-integrated with low-voltage advanced CMOS technologies. The device electrical characteristics show: (i) a switching time of 100ns at 1V, (ii) an excellent data retent...
In this work, a comprehensive investigation of disturb in HfO2-Resistive Random Access Memories (RRAM) integrated in an advanced 65nm technology is presented. The effects of the oxide thickness and RESET conditions on disturb immunity of the High-Resistance-State (HRS) are explored. Constant Voltage Stress is applied on a large amount of samples at...
The invention relates to a method for functionalizing an electrically conductive substrate, which is not a substrate made of gold, via a layer of chemical compounds, said method comprising the following steps: a step in which the electrically conductive substrate is placed in contact with chemical compounds comprising at least a disulfide terminal...
In this paper we propose to optimize the 1T silicon nanocrystal (Si-nc) memory cell in order to reduce the energy consumption for low power applications. Optimized Channel Hot Electron Injection (a 4.5V programming window is reached consuming 1nJ) and Fowler-Nordheim programming are analyzed and compared. The tunnel oxide thickness, Si-ncs area cov...
In this paper we propose the optimization of the programming operation scheme of Silicon nanocrystal (Si-nc) memories in order to reduce the energy consumption for low power applications. Using the program kinetic characteristics and a dynamic current measurement method, the programming window and the energy consumption during Channel Hot Electrons...
In Flash-like memory technologies, the replacement of the continuous polysilicon gate by silicon nanocrystals enables improving reliability thanks to discrete charge trapping within nanocrystals. In this context, this paper deals with the extraction of some physical parameters on silicon nanocrystals dedicated to non-volatile memories. An optimized...
Increasing demand for Non-Volatile Memories (NVM) requires sustained research efforts in Flash memories cell size reduction, production cost reduction and performances improvements. Silicon Nanodots used as discrete charge traps in replacement of a continuous polysilicon floating gate are considered as an optimized solution to improve Flash memorie...
In this paper, the evolution, limits and challenges of charge-storage Silicon Non Volatile Memory technologies are presented, with a special attention for 3D architectures. Then, new resistive memory technologies are introduced. Main principles, challenges and opportunities are discussed. In particular, an overview of our recent research work on ph...
In this paper, memory devices integrating a double layer of silicon nanocrystals (Si-ncs) as a trapping medium and a HfAlO-based control dielectrics are presented. We will show that the use of two stacked Si-nc layers significantly improves the memory window compared with the single Si-nc layer devices, without introducing anomalies on the charging...
The use of diblock copolymers PS-b-PMMA self-assembly for patterning silicon nanopillars and nanowires is presented in this paper. In particular, formation of PMMA cylinders in a PS matrix is studied. After removal of the PMMA domains, a porous PS template is obtained. This PS template must then be transferred to a hard mask highly resistant to pla...
Non-Volatile Memories (NVM) integrating silicon nanodots (noted SDs) are considered as an emerging solution to extend Flash memories downscaling. In this alternative memory technology, silicon nanocrystals act as discrete traps for injected charges.
Si-dots were grown by Low Pressure Chemical Vapor Deposition (LPCVD) on top of tunnel oxide. Dependi...
In this paper, an extensive investigation of hybrid molecular/Si field-effect memories is presented, where redox ferrocene (Fc) molecules play the role of the memory charge storage nodes. Engineering of the organic linkers between Fc and Si is achieved by grafting Fc with different linker lengths. The study shows a clear correlation between results...
We present in this paper a method to increase the density of nanocrystals (NCs) in a storage device having a discrete floating gate. The method consists of the growth, by reduced pressure chemical vapour deposition (RPCVD), of two superposed NC layers separated by a very thin deposited dielectric layer. The cross-sectional scanning electron microsc...
We present chemical vapor deposition of titanium nitride nanocrystals (ncs) on silicon nitride (SiN). Ncs are passivated in situ by a silicon shell and encapsulated in SiN. High density (3×1012 cm−2), crystalline and isolated ncs are observed by transmission electron microscopy and characterized by x-ray photoelectron spectroscopy. TiN ncs/SiN are...
A generic, CMOS compatible strategy for transferring a block copolymer template to a semiconductor substrate is demonstrated. An aluminum oxide (Al(2)O(3)) hard mask is selectively deposited by atomic layer deposition in an organized array of holes obtained in a PS matrix via PS-b-PMMA self-assembly. The Al(2)O(3) nanodots act as a highly resistant...
This chapter focuses on two emerging nanotechnologies developed to fabricate, organize and integrate nanomaterials (nanodots, nanowires) in nanoelectronics devices. The first one uses the natural properties of diblock copolymers to create (i) a hexagonal lattice array of vertical PMMA cylinders in a polystyrene (PS) matrix, or (ii) an ordered array...
Silicon nanocrystal (Si-nc) trapping layers offer several advantages on standard poly-Si floating gates, as improved data retention after endurance in particular at high temperatures, robustness toward oxide defects, two-bits per cell storage and full compatibility toward CMOS process. It has also been shown that coupling the Si-nc concept with hig...
In this papa, we present CVD (Chemical Vapor Deposition) growth and passivation of tungsten (W) and titanium nitride (TiN) nanocrystals (NCs) on silicon dioxide and silicon nitride for use as charge trapping layer in floating gate memory devices. NCs are deposited in an 8 inches industrial CVD Centura tool. W and TiN are chosen for being compatible...
In this paper, we will make a general overview of different technological approaches suitable for charge storage memories. Several solutions to extend the floating gate Flash memory technology to the 22nm nodes and beyond, are presented. In particular, new modules (discrete traps memories, and more specifically silicon nanocrystal memories), new ma...
In this work, memory devices integrating a double layer of silicon nanocrystals as trapping medium and a high-k HfAlO-based control dielectric are presented. We will show that the use of two stacked Si-nc layers significantly improves the memory window compared to the single Si-nc layer devices, without introducing dispersions on the charging dynam...
In this paper, a physical investigation of hybrid molecular/Si memory capacitor structures is proposed, where redox-active molecules act as storage medium. Fc and ZnAB<sub>3</sub>P porphyrin were grafted on (100) Si with both a direct bond and a chemical linker in order to investigate the electron transfer properties of the molecule/Si system. The...
In this paper we propose an experimental and theoretical analysis of hybrid Ferrocene/Si memory structures. Two main aspects are studied: the influence of the chemical linker length on Ferrocene/Silicon electron transfer rate, and the thermal stability of the hybrid devices. X-Ray Photoelectron Spectroscopy was used to analyse the chemical structur...
In this paper, silicon nanocrystals (Si-NCs) fabricated by Chemical Vapor Deposition (CVD) are successfully integrated in a 32 Mb ATMEL NOR Flash memory product, processed in a 130 nm technology platform. Different Si-NC deposition conditions are explored and the threshold voltage distributions of the arrays are correlated to the Si-NC size/dispers...
In this work, a physical and electrical investigation of hybrid molecular/Si memory capacitor structures is proposed, where redox active molecules act as storage medium. Ferrocene molecules were grafted on (100) Silicon either directly or with a chemical linker, in order to investigate the electron transfer properties of the molecule/silicon system...
We present the realization of hybrid silicon core/silicon nitride shell nanodots by Low Pressure Chemical Vapor Deposition (LPCVD) and their application as floating gate in Non Volatile Memory (NVM) devices. The LPCVD process includes three steps: nucleation using SiH4, selective growth of the silicon nuclei using SiH2Cl2 and finally selective grow...
In this paper, silicon nanocrystals (Si-NCs) fabricated by chemical vapor deposition (CVD) are, for the first time at our knowledge, successfully integrated in a 32 Mb NOR flash memory product, processed in a 130 nm technology platform. The large set of data measured on arrays clearly demonstrates the robustness of our process and integration schem...
In this work, data of a 32Mb Si-NC NOR flash memory product, fabricated in a 130nm ATMEL technology platform have been presented. Measurements have shown an average threshold voltage shift of 3V, without extrinsic bits even after cycling and data retention at 150degC. An in-depth study of gate disturb has been performed, focusing on the influence o...
This work presents TCAD simulations of NOR NC memories performed with commercial tools, which allow for a good understanding of the impact of the localized charge on both electrostatics and dynamics of the cell. The key role of the position of the trapped charges along the channel length on the threshold voltage shift has been put in evidence. Inde...
Integration of GaAs and InP with Si technology presents a huge potential interest. When realised, it will combine the superior electrical and optical properties of GaAs and InP with the mechanical and economical advantages of Si, including large integration density. To obtain such hybrid structures, heteroepitaxial growth has been investigated exte...
In this work we have investigated the feasibility of using ultrathin III–V films stuck on silicon as seed layers for subsequent epitaxial growths. The sticking is done by a thick viscous layer, which is assumed to act as an accommodating layer allowing the elastic relaxation of the initially strained III–V film. Two kinds of viscous layers have bee...
In microelectronics, photonics, opto-electronics, high frequency or high power device applications, the needs for specific
substrate solutions are more and more required. Smart Cut™ technology appears as the technological answer that enables the
industrial to provide engineered substrate solutions tailored to the applications. For instance a large...
Large band gap semiconductors will find more and more applications in such important fields as power electronics, high temperature electronics or optoelectronics where traditional semiconductors are not suitable. Very important efforts have been made in the last decade on the development of wide band gap materials. It is crucial for any industrial...
The general objective of this presentation is to demonstrate the great potential of two dimensional (2D) Photonic Crystals (PC) based on InP-membranes bonded onto silica on silicon substrates, with a special emphasis on the development of various classes of 2D PC microlasers. The basic building block consists in an InP (and related material) membra...
Wafer bonding technologies have been recognized to provide new substrates structures suitable for the development of Si power devices. Among the multiple examples that could be listed, the possibility to generate PN junctions without thick epitaxial growth and lateral devices onto dielectrically isolated substrates such as SOI (Silicon On Insulator...
The SmartCut process was first developed to obtain silicon-on-insulator (SOI) materials. Now an industrial process, the main
Unibond SOI-structure trends are reported in this paper. Many material combinations can be achieved by this process, because
it appears to enable the generic development of new structures. Several of the new structures combin...
With a view to investigating the feasibility of using ultrathin films as compliant substrates, we present some preliminary results concerning InAs<sub>0.25</sub>P<sub>0.75</sub> (0.8% compressively-stressed on InP) film stuck onto a Si host substrate via borophosphorosilicate glass (BPSG). In an attempt to study relaxation mechanisms without any li...
We report here on the bonding of a thin InP(001) layer onto a Si host substrate via silicon dioxide, to be used as a substrate for heteroepitaxy. With this end in mind, these new InP/SiO<sub>2</sub>/Si substrates were compared to standard InP substrates through the growth by Solid Source Molecular Beam Epitaxy of (lattice-matched) InP thick layers...
Graphite-lattice photonic crystal structures in InP-based heterostructures transferred onto silicon, including a multi-quantum well active layer, have been designed and fabricated. 1.5 μm vertical emission laser operation was observed at room temperature, with very low threshold (below 50 μW).
We report on 2D photonic crystal InP membrane micro-lasers transferred onto a silicon wafer. Two types of lasers are investigated: microcavities and defect-free structures, exploiting either conventional defect modes, or DFB-like modes. Room temperature low threshold laser operation has been performed for low sized devices.
We report results on hexagonal-shaped microlasers formed from two-dimensional photonic crystals (PCs) using InP-based materials transferred and bonded onto SiO<sub>2</sub>/ Si wafers. Two types of hexagonal cavities are investigated : single defect (one hole missing) cavities, so-called H1 cavities (1 μm in diameter) and two holes missing per side...
We present simulation and experimental results on hexagonal-shaped microcavities formed in two-dimensional (2D) photonic crystals (PC’s). The PC structures, realized with InP-based materials, are studied in two configurations : Air-suspended membranes (A type) and membranes supported by silica (S type). The optical properties of these microcavities...
Defectless two-dimensional photonic crystal structures have been fabricated by drilling holes in a thin multi-quantum-well InP-based heterostructure transferred onto a silicon host wafer. Extremely low group velocity modes, which correspond to the predicted photonic valence band edge, have been observed for different filling factors. Under pulsed o...
Nous avons réalisé des microcavités à cristaux photoniques à 2D sur une hétérostructure en InP reportée sur silicium. Les propriétés modales de ces structures ont été étudiées théoriquement et expérimentalement, en fonction de la taille de la cavité et du diamètre des trous du cristal photonique. Un pompage de ces structures en régime pulsé à tempé...
Metallic wafer bonding between SiC wafers and transfer of high quality 4H SiC thin film using the Smart-Cut® process is demonstrated. These substrates, developed for vertical SiC power devices applications such as Schottky diodes, involve metallic wafer bonding between SiC wafers as well as transfer of high quality thin film onto low cost SiC subst...
New In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As transferred-substrate high electron mobility transistors (TS-HEMTs) have been successfully fabricated on 2-in Silicon substrate with 0.12 /spl mu/m T-shaped gate length. These new TS-HEMTs exhibit typical drain currents of 450 mA/mm and extrinsic transconductance up to 770 mS/mm. An extrinsi...
We fabricated membranes which generally include InAsP/InP quantum wells that emit light around 1.5 μm. Depending on the structure studied, it can be used either as an efficient optical gain material (well suited for light emission), or as an active probe to insert light into PC structures (to study optical waveguides). Characterisation is performed...
