
Dr Shiromani Balmukund RahiIndian Institute of Technology Kanpur | IIT Kanpur · Department of Electrical Engineering
Dr Shiromani Balmukund Rahi
Ph. D.(Indian Institute of Technology Kanpur)
Looking for Collaborators/interested scholar for GAA/Nanosheet Field Effect Transistor-Design, Modeling and Application
About
61
Publications
32,690
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370
Citations
Citations since 2017
Introduction
• Ph.D.( Microlectrnics & VLSI) from the Department Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur.
• My research interests are: Nanoscale device, modeling, simulation (i.e. TFET, junctionless TFET), Negative Capacitance (NC) based FET devices, Simulation, Analysis and Development for low devices (special applications for Io T circuits), IoT Technology
Additional affiliations
December 2012 - present
June 2011 - December 2012
Syuash Institute of Information Technology Gorakhpur
Position
- Professor (Assistant)
Description
- 1-Year
Publications
Publications (61)
This book aims to provide information in the ever-growing field of low-power electronic devices and their applications in portable device, wireless communication, sensor, and circuit domains. . Negative Capacitance Field Effect Transistor: Physics, Design, Modeling and Applications, discusses low-power semiconductor technology and addresses state-o...
Bringing together experts and researchers from various facets of the VLSI domain, the book addresses the challenges posed by advanced low-power devices. This collaborative effort aims to propel engineering innovations and refine the practical implementation of these technologies. Specific chapters delve into intricate topics such as Tunnel FET, neg...
Complementary metal-oxide-semiconductor (CMOS) technology has reached its physical and technical limits during the last few years, and as a consequence, various architectures of field-effect transistors (FET) have been designed. The junctionless (JL) gate-all-around (GAA) MOSFET has been drawing considerable research attention. In addition, the com...
This book provides an overview of emerging semiconductor devices and their applications in electronic circuits, which form the foundation of electronic devices. Device Circuit Co-Design Issues in FETs provides readers with a better understanding of the ever-growing field of low-power electronic devices and their applications in the wireless, biosen...
Tunnel field effect transistor (TFET) is a gate-controlled, quantum FET device, exhibiting band-to-band tunneling (BTBT) transport phenomena with lower subthreshold swing (SS) than bulk MOSFET devices. Low ON-state current (ION) is an inherent problem with TFET devices. Various research groups are working to address the limitations due to low ON-st...
This book will give insight into emerging semiconductor devices from their applications in electronic circuits, which form the backbone of electronic equipment. It provides desired exposure to the ever-growing field of low-power electronic devices and their applications in nanoscale devices, memory design, and biosensing applications.
Tunneling Fi...
This book will provide an overview of emerging semiconductor devices and their applications in electronic circuits design, which form the foundation of electronic devices. Device Circuit Co-design Issues in FETs provides readers with a better understanding of the ever-growing field of low-power electronic devices and their applications in the wirel...
Nanosheet field effect transistor (NSFET) has emerged as a promising candidate to replace FinFET devices at sub-7 nm technology nodes and for different SoC applications. In this work, we have investigated the DC properties of 3D vertically-stacked NSFET including the impact of self-heating effect (SHE) and also the influence of geometry scaling. Th...
A tunnel field effect transistor (TFET) is a gate-controlled, band to band tunneling (BTBT) transport of charge carriers having low subthreshold swing(SS < 60 mV/decade|T = 300K). With TFETs, low-ION is a built-in problem which limits its adaptability to high-speed, low-power uses. To overcome this limitation, a conventional double-gate TFET was co...
The goal of this book, titled "Device Circuit Co-design Issues in FETs," is to provide readers with a better understanding of the ever-growing field of low-power electronic devices and their applications in the wireless, biosensing, and circuit domains. The area of low-power devices and circuits has gained popularity on a global basis due to the ne...
The requirement of small, portable and cheap electronic equipment is increasing day by day. Consequently, new semiconductor devices are explored by the researchers incessantly to fulfill the consumer demand. This book will give an insight to the emerging semiconductor devices from their applications in electronic circuits which are the backbone of...
The goal of this book, titled "Device Circuit Co-design Issues in FETs," is to provide readers with a better understanding of the ever-growing field of low-power electronic devices and their applications in the wireless, biosensing, and circuit domains. The area of low-power devices and circuits has gained popularity on a global basis due to the ne...
The goal of this book, titled "Device Circuit Co-design Issues in FETs," is to provide readers with a better understanding of the ever-growing field of low-power electronic devices and their applications in the wireless, biosensing, and circuit domains. The area of low-power devices and circuits has gained popularity on a global basis due to the ne...
In this article, a reliable static random access memory (SRAM) circuit design is proposed for improved thermal and electrical performance at 5-nm technology nodes. The proposed SRAM circuit is developed by incorporating bottom-up approach (from device level to circuit level). The proposed device/circuit design utilizes high thermal conductivity and...
In this article, a reliable static random access memory (SRAM) circuit design is proposed for improved thermal and electrical performance at 5-nm technology nodes. The proposed SRAM circuit is developed by incorporating bottom-up approach (from device level to circuit level). The proposed device/circuit design utilizes high thermal conductivity and...
In this article, a reliable static random access memory (SRAM) circuit design is proposed for improved thermal and electrical performance at 5-nm technology nodes. The proposed SRAM circuit is developed by incorporating bottom-up approach (from device level to circuit level). The proposed device/circuit design utilizes high thermal conductivity and...
Within this paper, a total optoelectronic simulation of a PIN photodiode structure was presented. The microlens structure has been introduced on the top of the PIN photodiode to compensate the low sensitivity level of the sensor. Finite-Difference Time-Domain (FDTD) method has been used to estimate the optical generation inside the active device. O...
In the present-day scenario of low-power electronics, there is a steady and increasing need for an adequate device that can counteract the power dissipation issue due to the consistent scaling of device dimensions. For this purpose, the evolution of low subthreshold swing (SS) based devices, especially with the negative capacitance (NC) techniques,...
This book gives insight into the emerging semiconductor devices from their applications in electronic circuits. It discusses the challenges in the field of engineering and applications of advanced low-power devices.
Emerging Low-Power Semiconductor Devices: Applications for Future Technology Nodes offers essential exposure to low-power devices, an...
This book gives insight into the emerging semiconductor devices from their applications in electronic circuits. It discusses the challenges in the field of engineering and applications of advanced low-power devices.
Emerging Low-Power Semiconductor Devices: Applications for Future Technology Nodes offers essential exposure to low-power devices, an...
This book gives insight into the emerging semiconductor devices from their applications in electronic circuits. It discusses the challenges in the field of engineering and applications of advanced low-power devices. Emerging Low-Power Semiconductor Devices: Applications for Future Technology Nodes offers essential exposure to low-power devices, and...
Tunnel FET is a field‐effect transistor, conceived from a P‐I‐N diode structure. It consists of a lower subthreshold slope than conventional MOSFET due to band‐to‐band tunneling. Due to the lower subthreshold slope, it has been advocated as a prospective low‐power device. This book chapter presents double gate tunnel FET (DGTFETs), drain‐voltage (I...
This chapter addresses overall memory design techniques for future technology nodes. In the introduction, the memory structures for next-generation memory are covered, and their advantages over conventional memory structures are addressed. Then, three main factors for memory design—low power, large memory margin, and long retention (3Ls)—are explai...
Tunnel FET is one of the promising devices advocated as a replacement of conventional MOSFET to be used for low power applications. Temperature is an important factor affecting the performance of circuits or system, so temperature associated reliability issues of double gate Tunnel FET and its impact on essential circuit design components have been...
In the present research article, we have proposed an analytical compact model for nanowire Junctionless Gate-All-Around (JLNGAA) MOSFET validated in all transistor's operation regimes. The developed model having an analytical compact form of the current expressions, based on surface potential (Φ S), obtained from approximated solutions of Poisson's...
This chapter addresses overall CMOS design techniques for the future technology nodes (especially, sub 7-nm node technology). In the introduction, the emerging new materials and novel structures for the next-generation CMOS device are covered, and their advantages and disadvantages over conventional CMOS devices are addressed. Then, three main fact...
In semiconductor industry, at nanoscale dimensions, numerous field effect devices have been proposed and investigated for further improvement in performance of low power circuit and system. In the present research report, a novel low power FET device structure namely: Surrounding Gate Triple Material Heterojunction Tunnel Field Effect Transistor (S...
Power consumption is the major concern for conventional CMOS based integrated circuit and systems. Since there is a scope of lowering supply voltage with steep-subthreshold swing field effect transistor (FET) devices, it has been advocated as a suitable candidate for future highly energy-efficient circuits and systems. Among all the developed and p...
This chapter focuses on double gate (DG) Tunneling Field Effect Transistor (TFET), having band engineering and high ‐ k dielectrics. The basic structure of TFET device is derived and developed by p‐i‐n diode, containing two heavily doped degenerated semiconductor “p” and “n” regions and lightly doped intrinsic “i” region, respectively. The chapter...
TCAD Simulations for 30 nm double gate tunnel field effect transistor (DGTFET) reports steeper subthreshold swing, SS ~ 15 mV/dec, ION ~ 10–4 A/µm, and low off-state current IOFF ~ 10−15A/µm as desirable parameters for low voltage applications. The unity gain frequency (fT) increases with Vgs and maximizes at 5.2 × 1011 Hz for Vgs = Vds = 0.7 V. It...
The present research letter is dedicated to a detailed analysis of a double-gate tunnel field-effect transistor (DG-TFET). The DG-TFET provides improved on-current (I ON) than a conventional TFET via band-to-band (B2B) tunneling. However, DG-TFET is disadvantageous for low-power applications because of increased off-current (I OFF) due to the large...
INTRODUCTION The adoption of cloud services in the semiconductor industry promises to bring enhanced performance and increased productivity to the industry. Cloud-based supply chain management, for example, can help these organizations adapt to rapidly changing requirements in the current competitive environment. These services also improve informa...
Increased static and dynamic power dissipation in the integrated circuits (ICs) are the main obstacle for growing demands of smart phones and laptops, which require semiconductor devices having low power operation. As the conventional MOSFET has a thermodynamic limit of 60 mV/decade at 300 K on subthreshold slope (SS), so the device based on the me...
In the rapidly changing world, the exponential growth in the semiconductor sector has
played a significant role in our daily life through the use of electronic products, like smart phone, laptop etc. The growth in the semiconductor industry has led to the compactness of electronic products with more functionalities, lower power consumption and high...
Cloud computing provides a way to integrate and share information on a real-time basis across an organization. The current organizations are adopting the cloud services to gain competitive advantage in real-time data sharing. To meet the current demand in semiconductor industries, they must develop better techniques to produce electronic products a...
Cloud computing provides a way to coordinate and share relevant information and data on real-time basis over an organization. The adoption of cloud services is one of the most emerging technological advances in the practice of current competitive business environment. The research done in this article is based on the analysis of the data obtained f...
Gate dielectric materials play a key role in device development and study for various applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials on the ON-current (\(I_{\mathrm{ON}}\)) and OFF-current (\(I_{\mathrm{OFF}}\)) of the heterogate junctionless tunnel field-effect transistor (FET). The heterogate conc...
Displacement Vector Continuity Technique for Optimized Electric Field in JL-TFET
In the present work, the performance of a heterostructure double gate junctionless tunnel FET (HJLDGTFET) having a tunable source bandgap has been analyzed using a 2D simulation technique. The
tunable source HJL-DGTFET shows a high ON-current (z6.5�10
�5
Amm�1
) and a very low OFFcurrent (z4.8�10
�17
Amm�1
). The device shows a point subthreshold s...
In this paper physics based analytical model for threshold voltage of nanoscale biaxial strained nMOSFET has been presented. The maximum depletion depth and surface potential in biaxial strained–Si nMOSFET is determined, taking into account both the quantum mechanical effects (QME) and effects of strain in inversion charge sheet. The results show t...
In this paper, we present improved device characteristics of Junctionless Tunnel Field Effect Transistor (JLTFET) with Si and SiGe hetero-structure. Optimization of device is done for low power applications. Heterojunction engineering is done to optimize position of Si:SiGe junction. Subsequently, band gap engineering is incorporated using variatio...
For the first time, we investigate the temperature effect on AlGaAs/Si based hetero-structure junctionless double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute device for
ultra scaled deep-submicron CMOS technology, having very good device characteristics such as an improved subthreshold slope (< 60...
We investigate the quantum-mechanical effects on the electrical properties of the double-gate junctionless field effect transistors. The quantum-mechanical effect, or carrier energy-quantization effects on the threshold
voltage, of DG-JLFET are analytically modeled and incorporated in the Duarte et al. model and then verified by
TCAD simulation
We propose a heterostructure junctionless tunnel field effect transistor (HJL-TFET) using AlGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain side. The whole AlGaAs/Si region is heavily doped n-type. The proposed HJL-TFET uses two isolated gates (named gate, gate1) with two di...
In this paper we have proposed an optimal design for a hetero-junctionless tunnel field effect transistor
(TFET) using HfO2as a gate dielectric. The device principle and performance are investigated using a 2D
simulator. During this work, we investigated the transfer characteristics, output characteristics,
transconductance, Gm, output conductance,...
In this paper, a physics based model of inversion charge sheet of nanoscale NMOSFETs has been presented. The model is formulated for nanoscale biaxial strained silicon NMOSFET including quantum mechanical effect (QME). The QME is splitting of conduction band due to very thin oxide (t ox) and very large doping concentration of ultra small geometry o...
In this paper physics based analytical model for threshold voltage of nanoscale biaxial strained nMOSFET has been presented. The maximum depletion depth and surface potential in biaxial strained–Si nMOSFET is determined, taking into account both the quantum mechanical effects (QME) and effects of strain in inversion charge sheet. The results show t...
Questions
Questions (38)
Dear friend, any interested scholar can put a message , if interested to discuss on " Cryogenics application based on subthreshold swing FETs"
at email id : sbrahi@gmail.com.
Dear scholar, can we interface, MATLAB and Silvaco?? .
Any idea, for suggestion and guidance welcome.
As scaling is pushed beyond 5nm, the FinFET and related family members is expected to run out of steam. Experts always suggest new FET structures. Technical resource is a big challenge for scholars/scientists. Is SILVACO-TCAD will be helpful to study ultra-scale FET structures. If no please suggest available tools.
Is SILVACO-TCAD simulation of is it doable for analysis?
Dear all friends,
Hope you are doing well, safe and healthy. Protect you, your family and team to new Covid-19 Variant ” OMicron"
Please suggest, Is NC- tunnel FET practically suitable for Neuromorphic Computing applications?
Dear all friends,
Hope you are doing well, safe and healthy. Protect you, your family and team to new Covid-19 Variant ” OMicron"
Please suggest, Is tunnel FET practically over take the limitations of Conventional CMOS Low Power Technology Limitations?
Dear scholar, I want to extract/ find data from publish article for calibration.
See the attached id-VG. I want data point Si TFET.
Plz help.
Dear scholar/scientist, as we know, when we plots Ids versus input gate voltage, Vgs in conventional,tunnel FET and NC FET. Commonly, we are getting, a maximum gm at particular input voltage Vgs. After maximum gm, it starts decreasing, why. Fell free discuss, in Researchgate platform as well as at following email address
Dear friends, Good morning. Hope you are doing well.
I want include symbols in origin file like “ delta” Please tell me.
Description. As we know that additional added FE (ferroelectric gate material) layer, amplifies the gate voltage of baseline FET structure. How I can calculate/determine Vint for knowing the dVin/dVgs i.e. rate of change Vin with respect to rate of change Vgs. Therotically this value is: dVin/dVgs > 1.
Please suggest at sbrahi@gmail.com
Dear friend, we are looking the impact of Ferroelectric materials on tunneling device. How, this helps to understand the behavioral change on conventional TFET.
Suggestion are most welcome the following email address:
Dear, scientists/ friends, we are using Silvaco for analysis for NC FET, please help us to investigate the impact of Ferroelectric effect, on NC FET. Which model help to investigate the Ferroelectric property and its impact on FET devices.
If any one working on similar research work, I am also interested to work jointly
For help and suggestion, friends are most welcome at the email address
sbrahi@gmail.