Domingo Benitez

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Verified

Domingo verified their affiliation via an institutional email.

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• PhD
• Full professor at University of Las Palmas de Gran Canaria

Problem statement. In the Computer Architecture course of Computer Science and Engineering undergraduate programs , there are often labs with simulation tools. This teaching method can give students misleading ideas about how hardware works because they are observing the behavior of a computer program, not the real hardware. In addition, the financ...

There is a growing interest in biomedical engineering in developing procedures that provide accurate simulations of the neural response to electrical stimulus produced by implants. Moreover, recent research focuses on models that take into account individual patient characteristics. We present a phenomenological computational model that is customiz...

A novel phenomenological epidemic model is proposed to characterize the state of infectious diseases and predict their behaviors. This model is given by a new stochastic partial differential equation that is derived from foundations of statistical physics. The analytical solution of this equation describes the spatio-temporal evolution of a Gaussia...

This paper compares methods for simultaneous mesh untangling and quality improvement that are based on repositioning the vertices. The execution times of these algorithms vary widely, usually with a trade-off between different parameters. Thus, computer performance and workloads are used to make comparisons. A range of algorithms in terms of qualit...

Many mesh optimization applications are based on vertex repositioning algorithms (VrPA). Since the time required for VrPA programs may be large and there is concurrency in processing mesh elements, parallelism has been used to improve performance. In this paper, we propose a performance model for parallel VrPA algorithms that are implemented on mem...

Many mesh optimization applications are based on vertex repositioning algorithms (VrPA). The execution times of these numerical algorithms vary widely, usually with a trade-off between different parameters. In this work, we analyze the impacts of six parameters of sequential VrPA on runtime. Our analysis is used to propose a new workload measure ca...

Many applications related to IoT cities such as building automation, traffic control, driver assistance, natural language translation, energy management, etc., are moving from servers to embedded computers while evolving at a rapid pace. The implementation of embedded applications for IoT cities is being facilitated by advances in processor archite...

We propose a new algorithm on distributed-memory parallel computers for our simultaneous untangling and smoothing of tetrahedral meshes [9, 10]. A previous parallel implementation on shared-memory computers is analyzed in [1]. The new parallel procedure takes ideas from Freitag et al. strategy [11]. The method is based on: partitioning a mesh, opti...

A parallel algorithm for simultaneous untangling and smoothing of tetrahedral meshes is proposed in this paper. This algorithm is derived from a sequential mesh optimization method. We provide a detailed analysis of its parallel scalability and efficiency, load balancing, and parallelism bottlenecks using six benchmark meshes. In addition, the infl...

A new parallel algorithm for simultaneous untangling and smoothing of tetrahedral meshes is proposed in this paper. We provide a detailed analysis of its performance on shared-memory many-core computer architectures. This performance analysis includes the evaluation of execution time, parallel scalability, load balancing, and parallelism bottleneck...

Many accelerator-based computers have demonstrated that they can be faster and more energy-efficient than traditional high-performance multi-core computers. Two types of programmable accelerators are available in high-performance computing: general-purpose accelerators such as GPUs, and customizable accelerators such as FPGAs, although general-purp...

The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits diminishing returns, while the higher cache latency hurts performance. This paper presents the Amorphous Cache (AC), a reconfigurable L2 on-chip cache aimed at improving performance...

The present invention relates to an electronic system architecture and whose internal structure can integrate the control of a robotic camera movements height / azimuth / pan in a home automation network compatible twisted pair Standards EN 50090 and ISO / IEC 14543. The apparatus comprises at least one microcontroller (4), a system memory (5), at...

An open question in chip multiprocessors is how to organize large on-chip cache resources. Its answer must consider hit/miss latencies, energy consumption, and power dissipation. To handle this diversity of metrics, we propose the Amorphous Cache, an adaptive heterogeneous architecture for large cache memories that provides new ways of configurabil...

We describe the analysis of an on-line pattern-recognition algorithm to dynamically control the configuration of the L1 data cache of a high-performance processor. The microarchitecture achieves higher performance and energy saving due to the accommodation of operating frequency, capacity, set-associativity, line size, hit latency, energy per acces...

High prediction bandwidth enables performance improvements and power reduction techniques. This paper explores a mechanism to increase prediction width (instructions per prediction) by predicting instruction traces. Our analysis shows that predicting traces including multiple branches is not significantly less accurate than predicting single branch...

Many authors have proposed power management techniques for general-purpose processors at the cost of degraded performance such as lower IPC or longer delay. Some proposals have focused on cache memories because they consume a significant fraction of total microprocessor power. We propose a reconfigurable and adaptive cache microarchitecture based o...

Adaptive processors can exploit the different characteristics exhibited by program phases better than a fixed hardware. However, they may significantly degrade performance and/or energy consumption. In this paper, we describe a reconfigurable cache memory, which is efficiently applied to the L1 data cache of an embedded general-purpose processor. A...

Accurate indirect jump prediction is critical for some applications. Proposed methods are not efficient in terms of chip area. Our proposal evaluates a mechanism called target encoding that provides a better ratio between prediction accuracy and the amount of bits devoted to the predictor. The idea is to encode full target addresses into shorter ta...

Reconfigurable architectures combine a programmable-visible interface and the high-level aspects of a computer's design. The goal of this work is to explore the architectural behaviour of remote reconfigurable systems that are part of general-purpose computers. Our approach analyses various issues arising from the connection of processors with FPGA...

The goal of this work is to explore the architectural behavior of FPGA- based coprocessors that are part of general-purpose computer systems. Our analysis shows maximum performance improvements of up to two orders of magnitude in comparison with current high-performance processors. However, the performance benefits exhibited by reconfigurable copro...

This paper describes a performance evaluation of image-processing applications on FPGA-based coprocessors that are part of general-purpose computers. Our experiments show that the maximum speed-up depends on the amount of data processed by the coprocessor. Taking images with 256×256 pixels, a moderate FPGA capacity of 10E+5 CLBs provides two orders...

In this paper we propose a system architecture which is hardware/software reconfigurable, modular, and intended to be a generic approach to partitioning reactive visual algorithms for implementation on highperformance multiprocessing systems integrated in robotic environments. We present a configurable and flexible parallel perception system that p...

Many vision tasks have stringent latency, throughput requirements, and real-time processing demand for greater parallelism. This paper describes a real-time Computer- Vision application that has been developed on a reconfigurable platform called RIPP10 from Altera. We use our simple, modular, reconfigurable and parallel specialized architecture cal...

Bio-inspired electronic coprocessor system for detecting colours in digital images. The invention relates to an electronic system whose architecture and internal structure enable digital images to be processed in real time. Its internal organization is inspired by the neurophysiology of natural systems possessing colour vision. This electronic stru...

This paper proposes an approach for teaching Computer Organization and Architecture which is based on building knowledge from the bottom up. Students should design three processors with increased complexity and measure their performances. These processor designs are assigned during a sequence of three 15-week courses and are implemented using a low...

This paper presents a modular architecture called DIPSA, which is intended to be used for building custom-made real-time Computer-Vision systems. It consists of four module types and each of them represents a family of circuits that perform specific visual tasks. Our architectural model proposes an algorithm-dependent methodology and makes good res...

In this paper a new learning algorithm for Fuzzy Radial Basis Function Neural Networks is presented, which is characterized by its fully-unsupervising, self-organizing and fuzzy properties, with an associated computational cost that is fewer than other algorithms. It is intended for pattern classification tasks, and is capable of automatically conf...

In this paper we present the chromatic neural-like network. It is a two-layer network architecture used in an image analysis system to learn objects classification tasks. Each processing unit in the hidden layer is considered as a network which codifies the color information at pixel level. The output layer makes a features analysis from the hidden...

Exponential filtering, together with an improved version of the iterative Fourier-transform algorithm, is applied to image reconstruction from one-dimensional infrared stellar speckle interferometry data. The performance of the method is checked first by computer simulations with both noiseless and noisy data and then with a realistic simulation of...

Exponential filtering, together with an improved version of the iterative Fourier-transform algorithm, is applied to image reconstruction from one-dimensional infrared stellar speckle interferometry data. The performance of the method is checked first by computer simulations with both noiseless and noisy data and then with a realistic simulation of...

The discriminatory additional information supplied by chromatic components of an image is useful for segmentation techniques that allow fast and efficient separation of the objects in a scene. We show a method that has two essential processes for separating and recognizing pans of a scene in the UVY visual chromatic space. In the learning process,...

The authors study the application of the phase retrieval algorithm suggested by Walker (1982) to 1-D short-exposure images obtained by infrared stellar speckle interferometry. To verify its performance, the algorithm has been tested previously with 1-D computer simulated speckle images.

The authors study the application of the phase retrieval algorithm suggested by Walker (1982) to 1-D short-exposure images obtained by infrared stellar speckle interferometry. To verify its performance, the algorithm has been tested previously with 1-D computer simulated speckle images.