Dimitrios Garyfallou

Dimitrios Garyfallou
University of Thessaly | UTH · Department of Electrical and Computer Engineering

Doctor of Philosophy

About

11
Publications
2,145
Reads
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25
Citations
Additional affiliations
September 2021 - present
University of Thessaly
Position
  • PostDoc Position
April 2019 - July 2019
Queen's University Belfast
Position
  • Research Assistant
September 2017 - June 2018
Queen's University Belfast
Position
  • Research Associate
Education
December 2015 - August 2021
University of Thessaly
Field of study
  • Computer and Electrical Engineering
October 2014 - November 2015
University of Thessaly
Field of study
  • Computer and Electrical Engineering
September 2009 - September 2014
University of Thessaly
Field of study
  • Computer and Electrical Engineering

Publications

Publications (11)
Conference Paper
Full-text available
With process technology scaling, accurate gate-level timing analysis becomes even more challenging. Highly resistive on-chip interconnects have an ever-increasing impact on timing, signals no longer resemble smooth saturated ramps, while gate-interconnect interdependencies are stronger. Moreover, efficiency is a serious concern since repeatedly inv...
Article
Full-text available
As process geometries shrink below 45 nm, accurate and efficient gate-level timing analysis becomes even more challenging. Modern VLSI interconnects are more resistive, signals no longer resemble saturated ramps, and gate input pins exhibit a significant Miller effect. Over recent years, the semiconductor industry has adopted current source models...
Conference Paper
Full-text available
The pessimistic nature of conventional static timing analysis has turned the attention of many studies to the exploitation of the dynamic data-dependent excitation of paths. Such studies may have revealed extensive dynamic timing slacks (DTS), however, they rely on frameworks that inherently make worst-case assumptions and still ignore some data-de...
Conference Paper
Full-text available
Manufacturing process variation in sub-20nm processes has introduced ever increasing overhead in Static Timing Analysis (STA) in order to guarantee the reliable operation of the circuit. Chip designers apply corner-based analysis and add guard-bands to design parameters in order to take into account the impact of process variation on timing. Howeve...
Conference Paper
Full-text available
The complexity of modern very large scale inte grated circuits renders circuit simulation very essential in the design process, as it is the only feasible way to verify circuit's behaviour prior to manufacturing. The heart of circuit simulation relies on the solution of huge systems resulting after the modelling using Modified Nodal Analysis. Matri...
Preprint
Full-text available
The rapid growth of circuit complexity has rendered Model Order Reduction (MOR) a key enabler for the efficient simulation of large circuit models. MOR techniques based on moment-matching are well established due to their simplicity and computational performance in the reduction process. However, moment-matching methods based on the ordinary Krylov...
Conference Paper
Full-text available
Second-order formulation using susceptance elements has become very effective in modeling on-chip inductive couplings. Several prior works have proposed model order reduction techniques for RLCK circuits, mostly based on balanced truncation (BT) and moment matching, providing reduced-order models (ROMs) that can be simulated over the whole frequenc...
Conference Paper
Full-text available
During the past decade, Model Order Reduction (MOR) has become key enabler for the efficient simulation of large circuit models. MOR techniques based on moment-matching are well established due to their simplicity and computational performance in the reduction process. However, moment-matching methods based on the ordinary Krylov subspace are usual...
Conference Paper
Full-text available
Signoff timing analysis is essential in order to verify the proper operation of VLSI circuits. As process technologies scale down towards nanometer regime, the fast and accurate timing analysis of interconnects has become crucial, since interconnect delay represents an increasingly dominant portion of the overall circuit delay. It is a common view...
Article
As process minimum feature sizes shrink, interconnect capacitance becomes a larger proportion of the total switched capacitance, thus standard cell and component placement increasingly affects power consumption. Therefore, minimizing the total interconnect wire length becomes a power reduction exercise as well. The final step of a standard cell pla...